Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—Layout Checklist
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
282 Order Number: 320068-005US
Table 98. CK410 Schematic Checklist
Signal Name
Trace Geometry and
Impedance
Length Requirements Comments
Note: See CK410 Clock Synthesizer/Driver Specification for more details
PCIF_0/ITP_EN Zo = 50
Ω +/- 10%
PCIF_1,
PCIF_2
Zo = 50
Ω +/- 10%
SRC[6:1]/
SRC[6:1]#
Zo = 50
Ω +/- 10%
DOT96/DOT96# Zo = 50
Ω +/- 10%
PCI[5:0] Zo = 50
Ω +/- 10%
CPU[1:0]/
CPU[1:0]#
Zo = 50
Ω +/- 10%
CPU_2/SRC_7,
CPU_2#/SRC_7#
Zo = 50
Ω +/- 10%
FS_A Zo = 50
Ω +/- 10%
FS_B/
TEST_MODE
Zo = 50
Ω +/- 10%
FS_C/TEST_SEL Zo = 50
Ω +/- 10%
REF Zo = 50
Ω +/- 10%
IREF Zo = 50
Ω +/- 10%
XTAL_IN/
XTAL_OUT
Zo = 50
Ω +/- 10%
• Connect to a 14.318-MHz
crystal, placed within 500
mils of CK410 device.
VTT_PWRGD#/
PD
Zo = 50
Ω +/- 10%
• Connect to Platform
VRMPWRGD signal after a
2ms delay.
• VTT_PWRGD# is a 3.3V
LVTTL input. It acts as a
level sensitive strobe to
latch the FS pins and
other multiplexed inputs.
After VTT_PWRGD#
assertiion, it becomes a
real time input for
asserting power down.
VDD_PCI[1:0],
VDD_CPU,
VDD_SRC[3:1],
VDD_REF,
VDD_48,
VDD_A
CK410 Power Pins
• Connect to VCC3
•See Section 8.3.4, “CK410
Power Plane Filtering” for
Power Filtering and
Decoupling guidelines.
VSS_48,
VSS_SRC,
VSS_CPU,
VSS_PCI[1:0],
VSS_REF
VSS_A
CK410 Ground Pins
• Connect to GND
•See Section 8.3.4, “CK410
Power Plane Filtering” for
Ground Filtering and
Decoupling guidelines.

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English