Intel
ยฎ
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 216
Gigabit Ethernet (GbE) InterfaceโIntel
ยฎ
EP80579 Integrated Processor Product Line
The RGMII interface gets Rx clock from the PHY and Tx clock from the MAC. The PHY
receives a 25 MHz reference clock from the board, and the PHY sources the 125 MHz
reference clock to the MAC. The RGMII outputs use 2.5V drivers that are 3.3V-tolerant.
Figure 136 shows the GbE block diagram with the signal connections in RGMII mode:
19.5.2 GbE Ethernet Interface โ RMII Mode
This section describes the GbE interface when the interconnect is designed for a RMII
interface.
In RMII mode, data is transmitted and received (TXDATA and RXDATA) with respect to
the MAC and PHY reference clock inputs, which in 10/100 Base T is 50 MHz.
Figure 137 shows the GbE signal connections used in RMII mode for 10/100 Base
connections. A 50 MHz external clock sources both the MAC and PHY reference clocks.
Figure 136. GbE RGMII Mode Signal Connection Block Diagram
PHY_REFCLK
1000 / 100 / 10 Base PHY
RGMII Signals
25 MHz
Reference Clock
GBE I/O
Vcc
MDIO
MDC
GTX_CLK
TX_EN
TXD[3:0]
RX_CLK
RX_DV
RXD[3:0]
GBEn_TxCLK
GBEn_RxCLK
GBE_REFCLK
GBEn MAC
MDIO
MDC
GBEn_TxCTL
GBEn_TxDATA[3:0]
GBEn_RxCTL
GBEn_RxDATA[3:0]
125 / 25 / 2.5 MHz
1.5 Kohm
VCCSUS25
Serial
EEPROM
EEDO
EECS
EEDI
EESK
125 MHz Clk
125 / 25 / 2.5 MHz
GBE I/O
Vcc
Vcc
2.5V +/- 5%
GBE_REFCLK_RMII
100 ohm