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Intel

EP80579 Integrated Processor Product Line—Component Quadrant Layout

Intel

EP80579 Integrated Processor Product Line

Platform Design Guide May 2010

37 Order Number: 320068-005US

4.0 Component Quadrant Layout

Figure 5 and Figure 6 show only general quadrant information for the EP80579

component, and not exact component pin placement. Designers must use the exact pin

assignment to conduct routing analysis. See the Intel

EP80579 Integrated Processor

Product Line Datasheet for exact ball assignment information.

Main Page

Table of Contents3
Revision History17
Introduction20
- Reference Documentation20
Reference Documents20
- Acronyms and Terminology21
System Overview24
- System Architecture Description24
  - EP80579 Features24
EP80579 Feature List25
- Development Board26
- Development Board Block Diagram26
  - Development Board Features28
Development Board Feature List28
- EP80579 External Clock Requirements30
Baseboard Requirements32
- Development Board Component Placement32
- Development Board Component Placement - Top View32
Assumptions for System Placement Example32
- Development Board Component Placement - Bottom View33
- PCB Recommended 10-Layer Stack-Up34
- Platform Stack-Up35
- Mounting36
Development Board Summary36
Component Quadrant Layout37
- Quadrant Layout (Top View)37
- Quadrant Layout38
- Quadrant Layout (Bottom View)38
High-Speed Design Concerns40
- Return Path40
- Decoupling Theory40
- Proper Decoupling Capacitor Placement with Respect to Vias40
  - Bulk Decoupling41
  - High-Frequency Decoupling41
- Serpentine Routing41
- Routing in a Serpentine Manner41
- Serpentine Spacing-Spacing to Reference Plane Height Ratio41
- High Speed Differential Routing Rules42
- Serpentine Line42
  - Serpentine Line Rules for Differential Signals43
  - Stitching Differential Signals between Layers43
- Tied Together for the same Potential Planes43
- Series Capacitor for Different Potential Planes43
- Stitching Vias Aligned with Signal Vias43
- Stitching for Layer Changes43
- Traces Routed Parallel to Plane44
  - Trace Segment Length Equalization, Bend, and Spacing45
- Trace Segment Length45
- Trace Mismatch45
  - Trace Mismatch and Compensation46
- Trace Length Mismatch Corners46
- Routing Examples of the Length Compensation #146
- Routing Examples of the Length Compensation #247
- DC Blocking Capacitor47
  - DC Blocking Capacitor48
- EMI Design Consideration48
  - Brief EMI Theory49
  - EMI Regulations and Certifications49
  - EMI Test Capabilities49
- Spread Spectrum Modulation Profile49
  - Spread Spectrum Clocking (SSC)50
- Impact of Spread Spectrum Clocking on Radiated Emissions50
- Cancellation of H-Fields through Inverse Currents50
  - Differential Clocking51
- Length Tuning Parameters51
- Length Tuning52
- Signal Length Solution Space with One Strobe52
- Signal Length Solution with Two Strobes52
  - Signal-To-Strobe Flight Time Relationships53
- Signal Length Solution Space with Furthest Apart Strobes53
- Signal Length Solution Space with Matched Strobes53
  - Flight Time Segment Analysis54
- Total Signal Length with Two Components54
- Package Trace Length Differences55
  - Bus Length Tuning Methodology56
- System Bus Tuning56
  - Compensating for Package Trace Length Differences56
- Example of PLC Compensation on the Motherboard56
- Common Layout Pit-Falls57
  - Signal Parallelism57
- Improper Via Sharing58
  - Via Sharing59
- Correct Via Connections59
  - Necking down60
- Improper Necking down60
- Correct Necking down61
- Signal Crossing Plane Splits62
  - Order Number: 320068-005US May62
  - Signals Crossing Plane Splits63
System Power Delivery Guide64
- Terminology and Definitions64
- Power Supply65
Power Supply Pins65
- Power Planes66
Power and Ground Planes66
- Power Requirements67
- Development Board Power Delivery Implementation67
- Power Delivery Guidelines69
  - Core Power (VCC_CPU)69
Development Board Power Delivery Voltage Definitions69
- Core Logic Voltage (V1P2)70
- IA-32 Core Frequency and Power Select (BSEL/V_SEL)70
- DDR2 Voltage (V1P8_DDR)70
- DDR2 Termination Voltage (DDR2_VTT)70
- Voltage (V1P8)70
- Gbe 2.5V (V2P5)70
- Vcc3)71
- Voltage (VCC50)71
- VCCRTC Reference71
- Standby Voltages71
- Auxiliary Voltages72
- Component Power Distribution Guidelines72
  - Core Power Distribution Guidelines72
  - General Switching Power Supply Design Recommendations72
- Voltage Regulator Multi-Phase Topology Example72
  - Voltage Regulator Design Recommendations73
- Buck Voltage Regulator Example73
- High Current Path with Top MOSFET Turned on73
- High Current Path During Abrupt Load Current Changes74
- High Current Path with Top and Bottom Mosfets Turned off (Dead Time)74
- High Current Path with Bottom MOSFET(S) Turned on75
  - Power Plane Filter Requirements77
Processor VCCA Decoupling Circuit Topology77
Analog/Bandgap Filter Topology78
- Analog and Bandgap Filter Layout Guidelines79
- Analog and Bandgap Filter Frequency Response79
Analog and Bandgap Filter Components79
- Thermal Power Dissipation80
Filter Frequency Response Specification80
- Decoupling Recommendations81
Types of Reset and Wake-Up from Power Saving States84
- Software Controlled Reset85
- CPU (IA-32 Core) Only Reset85
- Reset and Powergood Interface Implementation85
Power Management and Reset Interface84
- Reset and Powergood Distribution84
Powergood and Reset Interface85
- Powergood Interface86
- Reset Interface86
- Reset Sequence87
- Power Management88
  - Supported Power States88
Three Basic System Power States88
Clock Control States89
- Power Sequencing90
Platform System Clock91
- Platform System Clock Generation91
CK410 Clock Groups92
Platform System Clock Reference92
Ref92
Development Board Clocking Diagram93
- System Clock Groups94
  - HOST_CLK Group94
Source Shunt Termination94
Trace Spacing for HOST_CLK Clocks95
HOST_CLK Routing Guidelines95
- CLK100 (SRC Clock) Group96
Source Clock Topology to down Devices (Except PCI-E)97
100 Mhz SRC/SRC# Clock Routing Guidelines for down Devices(Except PCI-E)97
CLK100 Clock Group (SRC Clock) Topology98
100 Mhz SRC/SRC# Clock Routing Guidelines for PCI Express Slot/Component98
- CLK33 Group99
Trace Spacing for 100 Mhz SRC Clocks99
33 Mhz Clock Relationships99
Topology for CLK33 to down Devices100
Trace Spacing for CLK33 (PCICLK) Clock100
CLK33 Routing Guidelines to EP80579, FWH, and LPC down Devices100
- CLK14 Group101
Topology for Sharing CLK33 between Two down Devices101
CLK33 Routing Guidelines for Two down Devices101
- CLK48 Group102
CLK14 Group Routing Guidelines102
- CK410 General Design Guides103
  - Clock Driver Decoupling103
Topology for CLK14102
Trace Spacing for CLK14 (REFCLK) Clocks102
CLK48 Routing Guidelines103
- Clock Power Delivery104
- Decoupling Caps and Ferrite Beads104
Topology for CLK48 Group103
Trace Spacing for CLK48 (USBCLK) Clocks103
Clock Grouping for Decoupling / Filtering105
- CK410 Power Plane Filtering106
Clock Power Groupings for Decoupling / Filtering105
Decoupling and Filtering Per Clock Group106
Ground Flood on Layer 1 Underneath CK410108
Edge Decoupling Caps - Examples109
- Iref110
- EMI Constraints110
Decoupling Capacitors Placement and Connectivity110
DDR Terminology111
Supported DDR2 Device Densities and Widths111
System Memory Interface (DIMM)111
- Terminology and Definitions111
- Supported Configurations111
Supported DRAM Capacity for 64-Bit Mode112
Supported DRAM Capacity for 32-Bit Mode112
- Rules for Populating DIMM Slots113
  - Supported Rank Configurations113
Supported DDR2 Data Speeds113
Supported DIMM Populations113
Supported DDR2 Rank Configurations in Single and Dual DIMM Mode113
- DRAM Addressing114
256Mb Addressing114
1Gb Addressing115
- DDR2 DIMM Ordering Overview116
DDR-DIMM- Implementation116
Example of One Single-Rank DIMM Population116
- System Memory Design Guidelines117
Example of Two Single-Rank DIMM Population117
Example of Dual-Rank DIMM Population117
DDR2 Signal Groups118
- Package Length Compensation119
- Length Matching and Length Formulas119
- DDR2 Interface System Interconnect119
Length Matching Formulas between EP80579 and DDR2 DIMM119
- Topologies and Routing Guidelines120
DDR2 Interfaced System Interconnect120
Data Signal Daisy Chain Routing Topology120
Ddr120
Data and Strobe Signal Group Routing Guidelines121
Data/Mask/Strobe Signal Routing Topology Diagram121
Data and Strobe Signal Group Routing Guidelines122
Differential Clock Signal Mapping123
Ddr123
Example Length Matching for a Data Byte Lane123
EP80579-To-DIMM Interconnect DDR2 Clock Signals124
Clock Signal Group Routing Guidelines125
DDR2 Point-To-Point Clock Routing Diagram125
Clock Signal Group Routing Guidelines126
DDR2 Control Signal Group Routing Guidelines127
DDR2 Control Signals- Implementation127
Write Operation ODT Table128
Address and Command Signals129
Read Operation ODT Table129
DDR2 Address/Command Signal Group Routing Guidelines130
- Reset Pin Requirement131
- DC Bias Signals131
Address/Command Daisy Chain with Parallel Termination Topology Diagram130
DDR2 Address/Command Signal Group Routing Guidelines131
DDR_SLWCRES, DDR_RCOMPX, DDV_CRES, & DDR_CRES0 Routing Topology132
DDR_CRES1 and DDR_CRES2 Signal Connections132
DDR_VREF Generation Example Circuit133
- Decoupling Recommendations134
- Order Number: 320068-005US May135
- PCI Express Layout Design Guidelines136
PCI Express* Interface135
PCI Express* Interconnect136
- Board Stack-Up Consideration137
- Impedance Requirements138
Trace Width/Impedance Requirement for Stripline and Microstrip Layers138
- AC Coupling Requirements139
- Via Requirements139
Recommended PCI Express Stripline Trace Width/Spacing138
Recommended PCI Express Microstrip Trace Width/Spacing139
- Compensation Resistor Signals Guidelines140
- PCI Express Clocks Routing Guidelines140
- Topology 1 - EP80579 to PCI Express Connector140
PCI Express Compensation Signal Guidelines140
PCI Express Connector Routing (EP80579 Transmit)141
- Topology 2 - EP80579 to PCI Express Connector142
- With Logic Analyzer Connector142142
PCI Express Connector Routing (EP80579 Receive)142
PCI Express Connector with LAI Connector Routing (EP80579 Transmit)143
PCI Express Connector with LAI Connector Routing (EP80579 Transmit)144
- Topology 3 - EP80579 to PCI Express down Device145
PCI Express Connector with LAI Connector Routing (EP80579 Receive)145
PCI Express down Device Routing (EP80579 Transmit)146
PCI Express down Device Routing (EP80579 Receive)147
- Topology 4 - EP80579 to PCI Express down Device with Logic Analyzer Connector148
PCI Express down Device with LAI Connector Routing (EP80579 Transmit)148
PCI Express down Device with LAI Connector Routing (EP80579 Transmit)149
- Additional Considerations for PCI Express150
  - PCI Express I/O Devices150
  - Emi150
PCI Express down Device with LAI Connector Routing (EP80579 Receive)150
- PCI Express (JTAG) Boundary Scan Pins151
- Terminating Unused PCI Express Ports151
- Probing Differential Pairs151
No Connect Signals for Unused PCI Express Ports151
Serial ATA (SATA) Interface152
- SATA Interface152
  - General Routing and Placement152
SATA Layout and Routing Example153
- SATA Transmit and Receive Signals - Sata_Txp[1:0], Sata_Txn[1:0], Sata_Rxp[1:0], Sata_Rxn[1:0]154
Transmit and Receive Routing Guidelines154
SATA Tx and Rx Signal Routing Topology155
SATA PCB Routing156
- SATA Trace Separation157
- SATA Trace Length Guidelines and Pair Matching157
SATA Trace Spacing157
- SATA AC Coupling Requirements158
- SATA General Purpose Signals - SATA1_GP, SATA0_GP158
- SATA Clock Signals - Sata_Clkrefp, Sata_Clkrefn158
- Order Number: 320068-005US May158
- SATA_RBIAS/SATA_RBIAS# Connection158
Sata_Rbiasp/Sata_Rbiasn Connection158
- SATALED# Implementation159
- SATA Host Connector Placement Considerations159
SATALED# Circuitry Example159
SATA_RBIAS/SATA_RBIAS# Routing Summary159
SATA Cable 90º Bend Height Example160
SATA Host Connector Placement Region Recommendations160
SATA Host Connector Placement ATX Area B161
- Terminating Unused SATA Interface162
Example of Poor Host Connector Placement162
Minimum Host Connector Placement Spacing (from SATA Specification)162
Universal Serial Bus (USB) Interface164
- USB Interface164
- Layout Guidelines164
  - General Routing and Placement164
  - USB Differential Signals - Usbp[1:0], Usbn[1:0]165
Case 1, USB Routing Guidelines - EP80579 to Connector165
USB Trace Lengths from Controller to Connector166
Case 2, USB Routing Guidelines - EP80579 Front Panel Option166
USB Trace Lengths for EP80579 Front Panel Solution167
Case 3, USB Routing Guidelines - Optional Front Panel Solution167
USB Trace Lengths for Optional Front Panel Option168
Microstrip) Recommended USB Trace Spacing168
Stripline) Recommended USB Trace Spacing168
- Usb_Rbiasp/Usb_Rbiasn Connection169
USB 2.0 Trace Length Guidelines169
- Clock Signal -- USB CLK48170
- USB over Current Protection - OC[1:0]170
- Plane Splits, Voids, and Cut-Outs (Anti-Etch)170
  - VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)170
Usb_Rbiasp/Usb_Rbiasn Routing Summary170
- GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)171
- USB Power Line Layout Topology171
- EMI Considerations171
  - Common Mode Chokes171
Good Downstream Power Connection171
Common Mode Choke171
- Esd172
- Front Panel Solutions173
Front Panel Header Schematic175
Front Panel Header Pin-Out175
- Front Panel Daughter Card176
- Terminating Unused USB Interface176
Motherboard Front Panel USB Support176
Smbus 2.0 / Smlink Interface178
- Smbus Design Considerations178
- General Design Considerations179
- High Power/Low Power Mixed Architecture179
System Management Bus (Smbus) Interface178
- Smbus 2.0/Smlink Interface178
High Power/Low Power Mixed Suspend/Core Power Well Architecture179
- Calculating the Physical Segment Pull-Up Resistor180
- Enabled System Management Features (Optional)180
Bus Capacitance Reference Chart180
Bus Capacitance/Pull-Up Resistor Relationship180
- Enabled System Management Vendors (Optional)181
Enabled System Management Vendors181
- Development Board System Management Implementation182
Development Board System Management - Smbus Block Diagram183
- SIO Implementation184
System Management SIO Implementation185
Low Pin Count (LPC) Interface186
- LPC Interface186
- LPC Layout187
  - General Routing and Placement187
  - LPC Interface Routing and Topology187
LPC Interface Diagram187
Development Board LPC Interface Block Diagram188
Topology of LPC Interface188
- Clock Signals -- CLK33189
- Trusted Platform Module (TPM) Guidelines189
  - TPM Design Considerations189
Routing Recommendations189
- Motherboard Placement Consideration190
TPM 1.1/EP80579 Block Diagram190
TPM 1.2/EP80579 Block Diagram190
- Firmware Hub (FWH) Guidelines191
FWH VPP Isolation Circuitry192
Real Time Clock (RTC) Interface193
- RTC Interface193
  - RTC Crystal193
RTCX1 and SUSCLK Relationship in EP80579193
- External Capacitors194
External Circuitry for the RTC194
RTC Routing Summary194
- RTC Layout Considerations195
- RTC External Battery Connection196
- A Schottky Diode Circuit to Connect RTC External Battery196
- Internal Only RTC External RTEST# Circuit197
- Susclk197
RTEST# External Circuit for the RTC197
- RTC Well Input Strap Requirements198
Synchronous Peripheral Interface (SPI)199
- Terminating Unused SPI Port199
- SPI Interface General Routing Guidelines199
Serial Peripheral Interface Signal Description199
- SPI Routing Guidelines200
- Boot BIOS Selection200
SPI Single Flash Device Routing Summary200
- Serial Flash Vendors201
SPI Topology (System BIOS Only)200
Boot-Up Strapping Options (Flash)201
GPIO Pin Definitions202
- Development Board GPIO Usage203
- Interrupts204
General Purpose I/O (GPIO) and Interrupt Interface202
- GPIO Signals202
Interrupt Configurations - APIC Mode204
Serial Interface Unit (SIU/UART)206
- SIU (UART) Interface206
  - SIU Interface Signals206
  - SIU Interface Interconnect207
SIU Interface Interconnect208
Gigabit Ethernet (Gbe) Interface209
- Gbe MAC/LAN Interface Interconnect209
- Order Number: 320068-005US May209
- Frequency Requirements210
- Gbe MAC Interface Guidelines210
- Gigabit Ethernet Interface Signals210
Frequencies of All Input Clocks210
Gbe Controller/Lan Interface Interconnect210
Gben Pin Table211
- Gbe Interface - LAN Connect Interface Guidelines215
  - Gbe Ethernet Interface - RGMII Mode215
Gbe MAC Serial EEPROM Interface Signals215
Gbe MAC Management Data Interface Signals215
- Gbe Ethernet Interface - RMII Mode216
Gbe RGMII Mode Signal Connection Block Diagram216
Gbe RMII Mode Signal Connection Block Diagram217
- Gbe Transmit and Receive Topology218
  - Gbe Transmit Topology218
Gbe RGMII Transmit Path Clock Topology219
Gbe RGMII Transmit Path Clock Routing Guidelines220
- Gbe RGMII Transmit Path Data\Control Topology221
- Gbe Receive Topology222
Gbe RGMII Transmit Path Data\Control Routing Guidelines222
Gbe RGMII Receive Path Clock Topology223
Gbe RGMII Receive Path Clock Routing Guidelines224
Gbe RGMII Receive Path Data/Clock/Control Topology225
- Gbe Serial EEPROM226
- Wake on LAN226
- Gbe Rcomp226
Gbe RGMII Receive Path Data\Control Routing Guidelines226
- Crosstalk Considerations227
- Pull-Up Termination227
- General Gigabit Ethernet Design Guidelines227
IEEE 1588-2008 Hardware Assist Interface229
- Input/Output Signal Application230
Classic Clock Synchronization Example230
EP80579 IEEE 1588-2008 Hardware Assist Block Diagram232
- Input233
- Outputs233
- Board Design Tips233
Controller Area Network (CAN) Interface234
- Input/Output Signal Application235
CAN Physical Interface Example235
- Multipoint Topology236
  - Board Design Tips236
CAN Multipoint Topology236
Local Expansion Bus (LEB) Interface237
- LEB Chip Select Assignment237
- LEB Memory Size (LEB_SIZE) Strapping238
- LEB Interface Topologies238
  - LEB Interface Topology at 33 Mhz238
  - Chip Select Topologies239
Multi-Drop Topology Diagram239
Multi-Drop Topology Trace Lengths for the Development Board239
Chip Select Point-To-Point Topology Diagram240
Chip Select Point-To-Point Topology Routing Guidelines240
- Address Star Topologies241
- Data and Control Star Topology242
Address Signals Star Topology Diagram242
Data, and Control Signals Star Topology Diagram243
- Mezzanine Card Interconnect244
Address, Data and Control Star Topology Routing Guidelines244
Address, Data, and Control Signals Mezzanine Star Topology Diagram245
Address, Data and Control Star Topology Routing Guidelines245
- Input/Output Signal Application246
- Design Notes247
Time Division Multiplex (TDM) Interface248
- Development Board TDM Support248
- SLIC/CODEC Interface248
- Device Connection248
TDM to SLIC/CODEC Interface Example249
- Input/Output Signal Application250
- Design Notes250
Synchronous Serial Port (SSP) Interface251
- Development Board SSP Support251
- EP80579 SSP Interface251
SSP to Serial Flash Interface Example253
Sideband Signals254
- Cpuslp_Out#, Init33V_Out#, Nmi, Smi_Out#, Stpclk_Out, Rcin257
Routing Recommendations for Sideband Signals257
Debug Port Design Guide258
- Overview258
- Terms and Definitions258
- Routing Guidelines261
  - JTAG Routing Guidelines261
Termination after Last Receiver261
Termination Prior to Last Receiver261
- Observation Port Routing Guidelines262
TDI-TDO Routing262
- Hook Pins Routing Guidelines263
BPM5 and Bpm3_In Platform Circuit263
- C (SDA/SCL) Routing Guidelines265
- Power265
- System Connection265
XDP to EP80579 Signal Connections265
- Mechanical Specifications266
XDP Connector System Keep-Out Diagram267
Layout Checklist268
- Functional Signal Definitions268
Signal Type Definitions268
- Layout Checklist269
- CK410 Layout Checklist281
CK410 Schematic Checklist282
Schematics Checklist283
- Functional Signal Definitions283
Signal Type Definitions283
- Schematic Checklist284
- Power Supply Decoupling310
- CK410 Schematic Checklist312
Reference Design315
System Memory Interface (SODIMM)316
- Terminology and Definitions317
- Supported Configurations317
- A.2 Supported Configurations317
- Differences between Unbuffered SODIMM and Unbuffered DIMM317
Supported SODIMM Memory Capacity for 64-Bit Mode317
DDR Terminology317
- SODIMM System Memory Design Guidelines318
DDR2 Unbuffered SODIMM and Unbuffered DIMM Pin Comparison Table318
DDR2 Signal Groups319
Length Matching Formulas between EP80579 and DDR2 SODIMM320
DDR2 Interfaced System Interconnect321
A-6 Data and Strobe Signal Group Routing Guidelines322
Data/Mask/Strobe Signal Routing Topology Diagram322
A-7 Clock Signal Group Routing Guidelines324
DDR2 Point-To-Point Clock Routing Diagram324
Write Operation ODT Table325
DDR2 Control Signals- Implementation326
Read Operation ODT Table326
DDR2 Control Signal Group Routing Guidelines327
Address and Command Signals327
A-12 DDR2 Address/Command Signal Group Routing Guidelines328
Address/Command with Parallel Termination Topology Diagram328
DDR_SLWCRES, DDR_RCOMPX, DDV_CRES, & DDR_CRES0 Routing Topology330
DDR_CRES1 and DDR_CRES2 Signal Connections330
- A.5 Decoupling Recommendations331
- Decoupling Recommendations331
- Clock Delay Programming and Write Levelization332
DDR_VREF Generation Example Circuit331
Write Levelization for Dual Rank Configuration332
System Memory Interface (Memory Down)333
- Terminology and Definitions333
- B-16 DDR Terminology333
- Supported Configurations334
B.2 Supported Configurations334
DDR Terminology334
Supported DDR2 Device Densities and Widths334
Supported DRAM Capacity for 64-Bit Mode334
- DRAM Addressing335
- B.3 DRAM Addressing335
512Mb Addressing335
- DDR2 Signal Groups336
Supported DRAM Capacity for 32-Bit Mode335
256Mb Addressing335
1Gb Addressing336
- Supported Memory Configurations337
- Order Number: 320068-005US May337
- Overview and Design Considerations338
- Figures338
- B-25 Memory Configurations Supported by the EP80579338
- B-26 Length Matching Formulas for Memory down Configuration338
Memory Configurations Supported by the EP80579338
Length Matching Formulas for Memory down Configuration338
B-28 Clock Signal Group Routing Guidelines340
Clock to Memory Device Mapping340
DDR2 Clock Signal Routing Topology (One Clock for Three Devices)340
B-29 Data and Strobe Signal Group Routing Guidelines342
DDR2 Data/DM/Ecc Byte Lane Topology342
DDR2 Data Strobe Routing (DQS/DQS#) Topology (One Strobe Per Byte Lane)342
Address and Command Signals344
DDR2 Address, Command and Control Signal Routing Topology344
B-31 DDR2 Address/Command Signal Group Routing Guidelines345
DDR_SLWCRES, DDR_RCOMPX, DDV_CRES, & DDR_CRES0 Routing Topology346

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