Intel
ยฎ
EP80579 Integrated Processor Product LineโDebug Port Design Guide
Intel
ยฎ
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
266 Order Number: 320068-005US
26.5 Mechanical Specifications
Figure 157 illustrates the target system volume that must be reserved for the ITP-XDP
to attach to the target system. It is recommended that the main ITP-XDP enclosure be
securely attached to the target system to avoid damage to the ITP-XDP and the target
system. Four 1/8 inch mounting holes are provided on the ITP-XDP to facilitate
attachment with screws or cable ties.
7 GND GND NA System 8 GND GND NA System
9 OBSDATA_A[0] BPM3 I EP80579 10 OBSDATA_C[0] Open NA
11 OBSDATA_A[1] BPM2 I EP80579 12 OBSDATA_C[1] Open NA
13 GND GND NA System 14 GND GND NA System
15 OBSDATA_A[2] BPM1 I EP80579 16 OBSDATA_C[2] Open NA
17 OBSDATA_A[3] BPM0 I EP80579 18 OBSDATA_C[3] Open NA
19 GND GND NA System 20 GND GND NA System
21 OBSFN_B0 Open NA 22 OBSFN_D0 BPM3_IN O EP80579
23 OBSFN_B1 Open NA 24 OBSFN_D1 Open NA
25 GND GND NA System 26 GND GND NA System
27 OBSDATA_B[0] Open NA 28 OBSDATA_D[0] Open NA
29 OBSDATA_B[1] Open NA 30 OBSDATA_D[1] Open NA
31 GND GND NA System 32 GND GND NA System
33 OBSDATA_B[2] Open NA 34 OBSDATA_D[2] Open NA
35 OBSDATA_B[3] Open NA 36 OBSDATA_D[3] Open NA
37 GND GND NA 38 GND GND NA System
39 PWRGOOD/HOOK0 PWRGOOD I System 40 ITPCLK/HOOK4 BCLK I System
41 TESTINb/HOOK1 Open NA 42 ITPCLK#/HOOK5 BCLK# I System
43 VCC_OBS_AB 1.8V NA System 44 VCC_OBS_CD 1.8V NA System
45 HOOK2 PCICLK I System 46 RESET#/HOOK6 RESET# I System
47 HOOK3 CLK REF I System 48 DBR#/HOOK7 DBR# O System
49 GND GND NA System 50 GND GND NA System
51 SDA SDA I/O System 52 TDO TDO I EP80579
53 SCL SCL O System 54 TRSTn TRST# O EP80579
55 TCK1 Open NA 56 TDI TDI O EP80579
57 TCK0 TCK O EP80579 58 TMS TMS O EP80579
59 GND GND NA System 60 GND
XDP_PRESE
NT#
OSystem
Table 95. XDP To EP80579 Signal Connections (Sheet 2 of 2)
Pin XDP Signal Name
Target
Signal
I/O Device Pin
XDP Signal
Name
Target
Signal
I/O Device