Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 102
Platform System Clock—Intel
®
EP80579 Integrated Processor Product Line
8.2.5 CLK48 Group
The driver in the CLK48 group is the clock synthesizer USB clock output buffer,
USB_48. The receivers are the CLK48 input buffers on the EP80579.
Figure 62. Topology for CLK14
Table 23. CLK14 Group Routing Guidelines
Parameter Routing Guidelines Figure
Signal Group
CLK14: 14 MHz Clock -- LPC_14MHz_CLK,
ICH_14MHz_CLK
Reference Plane Ground Referenced
Layer Assignment Layers 8
Characteristic Trace Impedance (Zo) 50 Ω ±10% (single ended)
Nominal Trace Width 4.5 mils Figure 63
Nominal Trace Spacing
Edge to Edge within CLK14 Group:10 mils
Edge to Edge not in CLK14 Group:10 mils
Figure 63
Routing Length – L1: Clock Driver to Rs 0.1 in. max Figure 62
Routing Length – L2: Rs to EP80579 SIO 18 in. max Figure 62
REFCLK total length (L1+L2) (L1+L2) to EP80579 must be within 0.500
inches of (L1+L2) to SIO
Figure 62
Resistors Single Load: Rs = 43 Ω
±5%
Double Load: Rs = 33 Ω
±5%
Triple Load: Rs = 12 Ω
±5%
Figure 62
Skew Requirements (to other clock groups) None Figure 62
Figure 63. Trace Spacing for CLK14 (REFCLK) Clocks
L1
L2
Clock
Driver
Rs
SIO
EP80579
ICH_14M Hz
h
W
S1S1
REFCLK
Ground Plane