Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 321
System Memory Interface (SODIMM)—Intel
®
EP80579 Integrated Processor Product Line
A.4.5 Topologies and Routing Guidelines
A.4.5.1 DDR2 Data and Strobe Signals – DQ/DM/DQS
The Data and Strobe topology shown in Figure A-2 is the same for each Data Byte
Group (See Table A-4). The DQS signals must be routed as differential pair within inter-
pair skew of ± 10mils. All signals in same byte lane should be matched within 20 mils
of each other. (For example, DQS0[+/-], DQ[0..7] and DM0 are in the same byte lane).
All trace impedances should be 40 ohm± 10%. The parameters provided in Table A-6
are targeted for 40 ohm.
Figure A-1. DDR2 Interfaced System Interconnect
SODIMM
EP80579
Parallel Termination Resistors
VTT
Regulator
DDR2_VTT
DDR2
Memory
Controller
Command/Address
CS0#, CKE0, ODT0
CS1#, CKE1, ODT1
CLK0 / CLK0#
CLK1 / CLK1#
DQS[7:0]/DQS#[7:0]
DQ[63:0], DM[7:0]]