Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—Power Management and Reset Interface
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
90 Order Number: 320068-005US
While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the IA-32
core, and only serviced when the IA-32 core returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the IA-32 core will process snoops on the FSB and it will
latch interrupts delivered on the FSB.
7.3.1.3.4 HALT/Grant Snoop State
The IA-32 core will respond to snoop or interrupt transactions on the FSB while in Stop-
Grant state or in AutoHALT Power Down state. During a snoop or interrupt transaction,
the IA-32 core enters the HALT/Grant Snoop state. The IA-32 core will stay in this state
until the snoop on the FSB has been serviced (whether by the IA-32 core or another
agent on the FSB) or the interrupt has been latched. After the snoop is serviced or the
interrupt is latched, the IA-32 core will return to the Stop- Grant state or AutoHALT
Power Down state, as appropriate.
7.3.1.3.5 Sleep State
The Sleep state is a low power state in which the IA-32 core maintains its context,
maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep
state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the IA-
32 core will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin
should only be asserted when the IA-32 core is in the Stop Grant state. SLP#
assertions while the IA-32 core is not in the Stop-Grant state is out of specification and
may result in unapproved operation.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep
state will cause unpredictable behavior.
In the Sleep state, the IA-32 core is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP# or SYS_RESET#) are allowed on the FSB while the IA-32 core is in Sleep state.
Any transition on an input signal before the IA-32 core has returned to Stop-Grant
state will result in unpredictable behavior.
If RESET# is driven active while the IA-32 core is in the Sleep state, and held active as
specified in the SYS_RESET# pin specification, then the IA-32 core will reset itself,
ignoring the transition through Stop-Grant State. If SYS_RESET# is driven active while
the IA-32 core is in the Sleep State, the SLP# and STPCLK# signals should be
deasserted immediately after SYS_RESET# is asserted to ensure the IA-32 core
correctly executes the Reset sequence.
7.4 Power Sequencing
Refer to Intel
®
EP80579 Integrated Processor Product Line Datasheet for Power
Sequencing Timing Diagrams.

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English