Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—PCI Express* Interface
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
143 Order Number: 320068-005US
• L3 and L4 are the logic analyzer connector breakout regions on each side of the
connector.
• L5 is from the logic analyzer connector breakout region to the PCI Express
connector.
• LT is the main routing section that is from the EP80579 pin to the PCI Express
connector.
Table 51. PCI Express Connector with LAI Connector Routing (EP80579 Transmit)
Parameter Routing Guidelines Figure
Signal Group PEA0_Tn[7:0], PEA0_Tp[7:0] -
Reference Plane Ground Referenced -
Layer Assignment
Layers 3 or 8 (stripline)
Layers 1 or 10 (microstrip)
-
Characteristic Trace Impedance (Zo) 90 Ω ±10% (Differential) -
Nominal Trace Width
4.5 mils (stripline)
4.75 mils (microstrip)
Figure 87
Figure 88
Nominal Trace Spacing within a pair from
edge to edge
5.5 mils (stripline)
5.25 mils (microstrip)
Figure 87
Figure 88
Nominal Trace Spacing from edge of one
differential pair to edge of another
differential pair
The greater of:
• 18 mils or 3x dielectric thickness (stripline)
• 20 mils or 3x dielectric thickness
(microstrip)
Figure 87
Figure 88
Trace Length L1, L1’– EP80579 Breakout
region and to AC CAP via
Min = 0.75 in.
Max = 2.5 in.
Figure 92
Trace Length L2, L2’ – AC CAP via to logic
analyzer breakout region.
Min = 0.5 in.(stripline)
Min = 0.5 in. (microstrip)
Max = 5.5 in.(stripline)
Max = 6.0 in. (microstrip)
Figure 92
Trace Length L3, L3’ – Logic analyzer
breakout region.
Min = 3.5 in. (microstrip)
Max = 0.5 in. (stripline)
Max = 7.0 in. (microstrip)
Figure 92
Trace Length L4, L4’ – Logic analyzer
breakout region.
Max = 0.5 in. (stripline) Figure 92
Trace Length L5, L5’ – Logic analyzer
breakout region to PCI Express connector.
Min = 2.5 in. (stripline)
Max = 7.0 in.(stripline)
Figure 92
Trace Length LT– EP80579 pin to PCI
Express connector
LT = L1 + L2 +L3 + L4 + L5 (stripline)
LT = L1 + L2 +L3 (microstrip)
Figure 92
AC Blocking Capacitor–AC CAP 0.1 μF Figure 92
Length Tuning Requirements
Routing must remain on the same layer.
Maximum number of vias is 6 (stripline) and 4
(microstrip).
LT-LT’ = ±5 mils
Figure 92

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English