Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 104
Platform System Clock—Intel
®
EP80579 Integrated Processor Product Line
• The VSS pins should not be connected directly to the VSS side of the caps. They
should be connected to the ground flood under the part which is via’d to the ground
plane in order to avoid VDD glitches propagating out, getting coupled through the
decoupling caps to the VSS pins. This method has been shown to provide the best
clock performance.
• The ground flood should be via’d through the ground plane with no less than 12 to
16 vias under the part. It should be well connected.
• For all power connections, heavy duty and/or dual vias should be used.
• It is imperative that the standard signal vias and small traces not be used for
connecting decoupling caps and ground floods to the power or ground planes.
8.3.2 Clock Power Delivery
Designers must take special care to provide a quiet VDDA supply to the Ref VDD, VDDA
and the 48 MHz VDD. These VDDA signals are especially sensitive to switching noise
induced by the other VDDs on the clock chip. They are also sensitive to switching noise
generated elsewhere in the system such as the processor voltage regulator. It is
recommended that a ground flood (Section 8.3.1, “Clock Driver Decoupling” on
page 103) be placed directly under the clock chip to provide a low impedance
connection for the VSS pins. In addition, power vias should be distributed evenly
throughout the ground flood.
Note: For all power connections to planes, decoupling capacitors, and vias, the maximum
trace width allowable and shortest possible lengths should be used to ensure the lowest
possible inductance.
8.3.3 Decoupling Caps and Ferrite Beads
Figure 66 shows the six different power groupings found on the CK410 and listed in
Table 25.
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