Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 220
Gigabit Ethernet (GbE) Interface—Intel
®
EP80579 Integrated Processor Product Line
19.6.1.2 GbE Transmit Data\Control Topology
The transmit Data and control signals included in the GbE transmit path topology
shown in Figure 139 are:
— GBEn_TXDATA[3:0]
—GBEn_TXCTL
All the transmit path Data and Control signals in a channel (see Figure 139) should be
length matched, routed on the same layer, and referenced to the Transmit Clock in
section Section 19.6.1.1. The transmit data and control signals do not need to be
length matched between channels, only within a channel. Table 84 provides routing
guidelines for the Transmit Data and Control signals.
Table 83. GbE RGMII Transmit Path Clock Routing Guidelines
Parameter Routing Constraints
Routing Layer Stripline Microstrip
Reference Plane Ground Reference
Board Trace Impedance 55 Ω 55 Ω
Trace Width 3.75mils (L3/L8) 4.5mils (L1/L10)
Clock Spacing (e2e) 20 mils (min) 25 mils (min)
EP80579 Clock Tx Breakout Length
(LClk_Brk_out_tx)
0.5 inch (max) 0.5 inch (max)
Clock Tx Board Length
(LClk_Brd_route_tx)
min =1.0 inch
max = 7.0 inch
min =1.5 inch
max = 8.0 inch
PHY Clock Tx Breakin Length
(LClk_Brk_in_tx)
0.3 inch (max) 0.3 inch (max)
Total Tx Clock Routing (LClk_total_tx)
min =1.0 inch
max = 7.8 inch
min =1.5 inch
max = 7.8 inch
Pull Up Resistor T-Line (Lpull_up) 0.4 inch (max) 0.4 inch (max)
Pull Up Resistor (Rpull_up) 1.2 KΩ (5%) 1.2 KΩ (5%)
Breakout\Breakin Spacing (e2e) 4 mils (min) 4 mils (min)

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English