Intel
®
EP80579 Integrated Processor Product Line—High-Speed Design Concerns
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
42 Order Number: 320068-005US
Routing a transmission line in a serpentine manner is sometimes necessary to properly
match lengths between nets. It is important to properly control the serpentine to avoid
signal integrity and timing problems. The primary impact of a serpentine-routed trace
is an observed decrease in the flight time when compared to a straight trace of equal
length. This decrease in the flight time is a result of the crosstalk between parallel
sections of the serpentined net. As the signal travels down the transmission line, a
component of the signal follows the transmission line and behaves as though it were a
straight line with no serpentine. However, another portion of the energy propagates
perpendicular to the parallel routed portions of the serpentined net via the mutual
capacitance and mutual inductance. This creates an extra mode that arrives at the
receiver significantly earlier than the other component of the signal. When the coupling
between parallel sections is high, significant timing skew may occur when attempting to
match trace lengths on a bus. Furthermore, when the coupling is very high, significant
signal integrity problems may result.
Serpentine routing requirements are defined using two parameters, as depicted in
Figure 9. Parameter “S” is the distance between the two segments of the serpentined
trace. Parameter “H” is the distance between the signal and the referenced plane. The
ratio is specified as S/H. For the EP80579 stack-up this ratio is typically 3:1. Check the
guidelines for each interface to ensure the proper ratio is being used.
5.4 High Speed Differential Routing Rules
The rules in the following sections pertain to high speed differential signals such as the
SATA and the PCI Express* signals.
Figure 8. Routing in a Serpentine Manner
Figure 9. Serpentine Spacing-Spacing to Reference Plane Height Ratio
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