Intel
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EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 203
General Purpose I/O (GPIO) and Interrupt InterfaceโIntel
ยฎ
EP80579 Integrated Processor
Product Line
17.1.1 Development Board GPIO Usage
The Development Board has all unused GPIO signals connected to headers. Some
multiplexed GPIO signals may not be connected to the headers if they are used for
alternate functions.
Table 76 provides a list of how the GPIO signals are used in the Development Board.
GPIO[27] I/O GPIO IRQ39 Multiplexed with IOAPIC IRQ39
GPIO[28] I/O GPIO IRQ30 Multiplexed with IOAPIC IRQ30
GP29_SATA1GP I GPI SATA1GP Multiplexed with SATA1GP
GPIO[30] I GPI IRQ31 Multiplexed with IOAPIC IRQ31.
GPIO[31] I GPI IRQ32 Multiplexed with IOAPIC IRQ32.
GPIO[33] I/O GPIO IRQ33 Multiplexed with IOAPIC IRQ33.
GPIO[34] I/O GPIO IRQ34 Multiplexed with IOAPIC IRQ34.
GPIO[40] I GPI IRQ35 Multiplexed with IOAPIC IRQ35.
GP41_LDRQ[1]# I LDRQ[1]# GPIO[41]
LDRQ[1]# multiplexed with
GPIO[41]
GPIO[48] O GPO N/A Unmultiplexed
Table 75. GPIO Pin Definitions (Sheet 2 of 2)
Signal(s)
I/O Type
(Default
Mode)
Function
(Default
Mode)
Alternate
Mode
Description
Table 76. Development Board GPIO Usage (Sheet 1 of 2)
Pin Name
I/O
(Default
Mode)
Signal Name
Mode of
Operatio
n
Function
GPIO[0] I T_GPIO[0] GPI Header
GPIO[1] I T_GPIO[1] GPI Header
GP2_PIRQE_N I T_GPIO[2] GPI Header
GP3_PIRQF_N I T_GPIO[3] GPI Header
GP4_PIRQG_N I T_GPIO[4 GPI Header
GP5_PIRQH_N I T_GPIO_5_FPGA_IN_5 GPI FPGA_IN_5
GPIO[6] I T_GPIO_6_FPGA_IN_6 GPI FPGA_IN_6
GPIO[7] I T_GPIO_7_FPGA_IN_7 GPI FPGA_IN_7
GPIO[8] I T_GPI8_SLEEP_WAKE_N GPI Sleep Wake
GPIO[9] I T_GPIO_9_FPGA_IN_9 GPI FPGA_IN_9
GPIO[10] I T_GPIO_10_FPGA_IN_10 GPI FPGA_IN_10
SMBALERT_N I IMCH_SMBALERT_N GPI SMBus Alert
GPIO[12] I T_GPIO_12_FPGA_IN_12 GPI FPGA_IN_12
GPIO[13] I T_GPIO_13_FPGA_IN_13 GPI FPGA_IN_13
GPIO[14] I T_GPIO_14_FPGA_IN_14 GPI FPGA_IN_14
GPIO[15] I T_GPIO_15_FPGA_IN_15 GPI FPGA_IN_15
GP16_IRQ24 I T_GPO16_HSS0_INT_N IRQ24 HSS0_INT_N
GP17_IRQ25 I/O T_GP017 GPIO T_GP017_HSS1/SPI Boot Select