Intel
ยฎ
EP80579 Integrated Processor Product LineโSerial Interface Unit (SIU/UART)
Intel
ยฎ
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
206 Order Number: 320068-005US
18.0 Serial Interface Unit (SIU/UART)
18.1 SIU (UART) Interface
The EP80579 provides two asynchronous Serial I/O Unit (SIU/UART) ports. These SIUs
are 16550-compliant with 16-byte transmit and receive buffers.
Both SIUs are full-function and can be used for debug purposes or connected to an
external modem. The ports have programmable Baud Rate generators. The maximum
baud rate supported by the SIUs is 115 Kbps. The SIUs can be connected point-to-
point. To ensure proper implementation, see the individual device design guide for the
peripheral to be connected.
18.1.1 SIU Interface Signals
Table 78. SIU Interface Signals (Sheet 1 of 2)
Signal Name
I/O
Direction
Description
UART_CLK I
48 MHz input clock to the SIU:
This clock is passed to the baud clock generation logic of each UART in the
SIU.
Note:
โข UART_CLK must be connected even when the ports are not used.
SIU_RXD[2:1] I/O
SERIAL INPUT for UART1 and UART2:
Serial data input from device pin to the receive port.
Note:
โข Must be pulled high through a 10 Kฮฉ resistor when the port is not
connected to an interfacing device
SIU_TXD[2:1] I/O
SERIAL OUTPUT for UART1 and UART2:
Serial data output to the communication peripheral/modem or data set. Upon
reset, the TXD pins are set to MARKING condition (logic 1).
Note:
โข Can be left as NC when the port is not connected to an interfacing device
SIU_CTS[2:1]# I/O
CLEAR TO SEND for UART1 and UART2: [Active low].
This pin indicates that data can be exchanged between EP80579 and the
external interface. These pins have no effect on the transmitter. These pins
could be used as Modem Status Input whose condition can be tested by the
processor.
Note:
โข Must be pulled high through a 10 Kฮฉ resistor when the port is not
connected to an interfacing device
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