Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 150
PCI Express* Interface—Intel
®
EP80579 Integrated Processor Product Line
10.2 Additional Considerations for PCI Express
10.2.1 PCI Express I/O Devices
Baseboard down PCI Express I/O devices typically require special layout techniques on
other data interfaces as well. Keep the considerations in this section in mind and
reference the appropriate design guides while performing the PCI Express layout.
10.2.2 EMI
As data is transmitted at higher frequencies, the spectrum of high-speed signals has
significant energy as the speed reaches several GHz. Minimizing and containing EMI is
challenging for wide band signals. There are two general principles for EMI reduction in
a system:
• Suppression of noise generation
Trace Length L2, L2’ – AC CAP to logic
analyzer breakout region.
Min = 0.5 in.
Max = 5.5 in.
Figure 97
Trace Length L3, L3’, L4, L4’ – Logic
analyzer breakout region.
0.5 in. (stripline) Figure 97
Trace Length L5, L5’ – Logic analyzer
breakout region to PCI Express device
breakout region.
Min = 2.5 in.
Max = 6.5 in.
Figure 97
Trace Length L6, L6’ – PCI Express
breakout region.
Min = 0.75 in.
Max = 2.0 in.
Figure 97
Trace Length LT– EP80579 pin to PCI
Express Device
LT = L1+L2+L3+L4+L5+L6 (stripline)
LT = L1+L2+L5+L6 (microstrip)
Figure 97
Length Tuning Requirements
Routing must remain on the same layer.
Maximum number of vias is 6 (stripline) and 4
(microstrip).
LT-LT’ = ±5 mils
Figure 97
Figure 97. PCI Express Down Device With LAI Connector Routing (EP80579 Receive)
Table 56. PCI Express Down Device with LAI Connector Routing (EP80579 Receive)
Parameter Routing Guidelines Figure
EP80579
PCI
Express*
Devi ce
L1
L2
AC CAP
LT = L1 + L2 + L3 + L4 + L5 + L6
LAI
Connector
L4L3 L5 L6
L1'
L2'
AC CAP
LAI
Connector
L4'L3' L5' L6'

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English