Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line—System Memory Interface (DIMM)
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
121 Order Number: 320068-005US
Figure 77. Data/Mask/Strobe Signal Routing Topology Diagram
Table 39. Data and Strobe Signal Group Routing Guidelines (Sheet 1 of 2)
Parameter
Routing Guidelines Figure
Data Byte Lane
Data & Data Mask Strobe
Signal Group Data & Mask (DQ & DM) Byte Strobe (DQS/DQS#)
Topology Daisy Chain Figure 76
Reference Plane Ground Referenced
Characteristic Trace Impedance
(Zo)
Single Ended Impedance = 40Ω ±10%
Layer assignment
• Layers 3/8
• Signals within the same Byte Lane must routed on
the same layer
Nominal Trace Width
A = See Package signal
B = 4 mils (Width), 4 mils (Spacing)
C = D = 6.5 mils
Figure 77
Trace-to-Trace spacing (e2e)
A = See Package Signals
B = 4 mils
C = D = 15 mils (min)
• Inter-pair Spacing:--
DQS/DQS# = 6 mils
(min)
• Pair-to-Pair Spacing:
15 mils (min)
Figure 77
Clearance from other signals 20.0 mils (min)
DIMM 0DIMM 1
EP80579
D
EP80579
Die
EP80579
Pin
Breakout
Routing
Dimm2Dimm
Routing
Package
Trace
EP80579
Pad
Board
Routing
ABC
L
PKG
L
BREAK
L
ROUTE
L
D2D