Intel
®
EP80579 Integrated Processor Product Line—Platform System Clock
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
91 Order Number: 320068-005US
8.0 Platform System Clock
The Development Board uses a single CK410 clock synthesizer, as well as DB800 x8
companion buffer solutions, to minimize jitter, improve routing, and reduce cost.
The CK410 provides three differential CPU host clock pairs and one selectable
differential CPU/SRC clock. All host clock pairs are frequency selectable at 100/133/
166/200/266/333/400 MHz.
The CK410 also provides six SRC (Serial Reference Clock) differential pairs to the
Development Board. The SRC clocks provide 100 MHz differential pair outputs for all of
the bus agents, including one for SATA devices and one 100 MHz differential output pair
SRC to the DB800. The DB800 companion differential buffer provides the 100 MHz
differential clocks for the PCI Express*. Figure 52 shows the implementation of the
CK410 bus clocks for the Development Board.
The Development Board design uses a CK410-compliant clock generator to supply the
primary clocks. Additional differential clocks are generated with the DB800 clock
synthesizer. The Development Board design also has various discrete clocks that are
not available in the CK410, such as GbE (25 MHz) and Local Expansion Bus (LEB) clock
(33 MHz).
8.1 Platform System Clock Generation
There are several external clock components shown in Figure 52. The first is the CK410
clock generator. This clock generator generates the following:
• Host_CLK: a 100/133 MHz reference clock which is used to generate the internal
FSB clock (controlled by the BSEL). This is a spread spectrum clock, so all clocks
derived from this will also be spread spectrum.
• CLK100 clock: a fixed 100 MHz reference clock which is used by the PCI Express,
SATA interface and DB800 companion differential buffer.
The CK410 also generates a number of other clocks, which are used by the IICH, such
as CLK33, CLK14, and CLK48.
The second clock component is the external 25 MHz crystal clock as a reference to the
GbE PHY; the GbE PHY uses this clock to generate a 125 MHz reference to the internal
GbE MACs. The Local Expansion Bus (LEB) also requires an external clock (33/80 MHz)
as reference to the LEB, and The TDM interface requires a 8.192 MHz that provides
external T1/E1 plug-on for mezzanines cards.
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