Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 257
Sideband Signals—Intel
®
EP80579 Integrated Processor Product Line
25.1 CPUSLP_OUT#, INIT33V_OUT#, NMI, SMI_OUT#,
STPCLK_OUT, RCIN#, A20GATE, IERR#
These signals are asynchronous and adhere to the routing recommendations and
topology recommended in Table 93.
IERR# CPU Sideband Output
EP80579 Internal Error:
• Asserted by the CPU as the result of an internal
error. Assertion of IERR# is usually accompanied by
a SHUTDOWN transaction on the FSB. This
transaction may optionally be converted to an
external error signal (for example, NMI) by
EP80579. The CPU keeps IERR# asserted until the
assertion of INIT33V_OUT# or EP80579 is reset
using SYS_RESET#.
• Connect to GPIO[40] to be used as IOAPIC IRQ35
• Pull up signal to Platform 3.3V (VCC3) power supply
using 10KΩ ± 5% resistor if used.
Note:
• This signal can be left as a no connect (NC) if not
used
Table 92. Sideband Signals (Sheet 4 of 4)
Signal Name Group Description
Table 93. Routing Recommendations for Sideband Signals
Signal Name Impedance
Width (W) /
Spacing (S)
Layer Notes
CPUSLP_OUT#
INIT33V_OUT#,
NMI,
SMI_OUT#,
STPCLK_OUT,
RCIN#,
A20GATE,
CPURST#,
CPUPWRGD_OUT,
IERR#
50Ω Stripline:
W = 4.5 mils
S = 15.0 mils
Microstrip:
W = 6.0 mils
S = 15.0 mils
Stripline
or
Microstrip
1, 2
Routing Guidelines
• The Sideband Signals are asynchronous signals and may be routed on either
the stripline or microstrip layers
• These signals may change layers, but this should be minimized as much as
possible
Notes:
1. W represents width of signal;
2. S represents spacing to any other signal.

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English