Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 45
High-Speed Design Concerns—Intel
®
EP80579 Integrated Processor Product Line
5.4.3 Trace Segment Length Equalization, Bend, and Spacing
The following are several general rules regarding the length matching and other factors
when routing high speed differential signal (see Figure 16 when reviewing these rules):
• Trace length matching between pairs is not required due to the embedded clock
and the pair-to-pair skew allowance; however, it is desirable to keep the length
differences small to minimize the latency.
• Trace segment length matching within the pair is required to ensure the trace
lengths are equal on a segment-by-segment basis.
• Examples of the segments could include the breakout areas, routes between the
two vias, routes between an AC coupling capacitor, and a connector pin, etc.
• When the ball-outs cause the traces to be staggered in the breakout region, add a
trace to equalize the length within the first 0.125 in.
• When a pair turns a corner, add a trace length to the inner side trace to equalize
the length within 0.125 inches of the corner.
• Do not equalize the net lengths only at the ends of a differential pair.
• Where a pair changes the layers, do not stagger the vias in the pair.
• Maintain the lateral symmetry between the traces as well as possible.
• When the traces are routed parallel to a plane edge, they must be at least 5x the
the dielectric height (5xH). See Figure 15.
• Avoid 90° bends.
Figure 15. Traces Routed Parallel to Plane
Plane 1
Trace
Dielectric
Height (H)
Plane 2
Trace
Plane 2
Plane
Edge
Plane 1
5xH
Top View
Cross Section
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