Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—Debug Port Design Guide
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
264 Order Number: 320068-005US
26.3.3.4 Reserved (HOOK[3])
This signal is reserved. No connection to this signal are required.
26.3.3.5 ITPCLK/ITPCLK# (HOOK[4:5]) Routing Guidelines
A copy of the system clock (BCLK) needs to be delivered to the XDP by a system-clock
component. ITPCLK (BCLK) and ITPCLK# (BCLK#) are used for:
• noise and synchronizer fault survivability
• as a frequency reference for some observation-port protocols
• as a frequency reference for run-control operations when enabled by the run-
control tool.
These operations may be disabled if ITPCLK is not connected or unavailable.
Route the reference clock differentially from the system-clock distribution component
to the HOOK[4:5] pins of the debug-port connector. Provide adequate source
termination of the clock traces at the clock driver. Route the signals using the
specification of the driver. There are no length-matching requirements for this clock
pair compared to any other signals in the target system.
Due to the variations in nomenclature, BCLK[0:1] is sometimes denoted as BCLK[p/n]
respectively. Thus, BCLK[0] = BCLK[p] = ITPCLK = ITP_BCLK_P = HOOK4 is the rising
edge for the beginning of every transaction. Conversely, BCLK[1] = BCLK[n] =
ITPCLK# = ITP_BCLK_N = HOOK5.
26.3.3.6 RESET# (HOOK6) Routing Guidelines
The RESET# signal is an input to the run-control tool. Run-control tools will not drive
RESET#. The run-control tool uses this signal to sense when a system reset has
occurred.
Route the EP80579 RESET# signal to the XDP RESET# pin through a 1k ohm isolation
resistor. Routing of this signal, before the isolation resistor, is left to the system
designers as part of the system design guides. On the debug-port side of the isolation
resistor, this signal has no length requirement.
The isolation resistor should be placed to remove any stub from the reset line by
placing the isolation-resistance pad directly, at any point, on the RESET# signal line.
There is no requirement from the point of view of the run-control tool, but the target
system will have signal-integrity issues with greater than a minimum stub on the
system RESET# line.
26.3.3.7 DBR# (HOOK7) Routing Guidelines
The DBR# signal is an output from the run-control tool to the system-reset control
logic. The run-control tool uses this signal to initiate a system reset. This reset
assertion must not cycle any power supplies on the target system nor may it alter the
PWRGOOD signal. The run-control tool will drive this signal with a silicon switch closure
to ground when a debug reset is requested.
Route this signal to any point within the system-reset topology that would initiate the
appropriate reset. Typical implementations route the DBR# signal to a reset controller
FPGA and a wire-OR function within the front-panel reset circuit
The pull-up value and location is not critical to the run-control tool but may be to the
receiver or other drivers if this signal is wire-ORed.

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English