Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 329
System Memory Interface (SODIMM)—Intel
®
EP80579 Integrated Processor Product Line
A.4.6 DC Bias Signals
The DC bias signals consist of DDR_SLWCRES, DDR_RCOMPX, DDR_CRES[2:0],
DDV_CRES, and DDR_VREF. The routing guidelines for these signals are described in
the following sections.
A.4.6.1 DDR_SLWCRES, DDR_RCOMPX, DRV_CRES, & DDR_CRES0
The DDR_SLWCRES, DDR_RCOMPX, DRV_CRES, and DDR_CRES0 signals are
compensation resistors for slew rate, impedance, and common return, respectively.
Intel recommends 20 mil wide traces with a minimum spacing of 12 mils from other
signals. When breaking out from the EP80579, maintain a minimum spacing of 4.5 mils
up to a maximum length of 500 mils. For the best signal integrity, minimize this length
as much as possible. Figure A-6 shows the routing topology for these signals.
L
BREAKOUT
Max = 0.8 in
L
ROUTE
Max = 4.0 in
L
BREAKIN
Max = 0.8 in
L
TERM
Max = 500 mils
• Trace length skews for the ADD/CMD signals to the termination
resistors (L
TERM
) should not exceed 200 mils.
On-Board Termination
Parallel Termination Resistor (Rtt) 100 Ω ±5% Figure A-5
Length/Skew Matching Rules
Length Tuning Requirements
• ADD/CMD signals should match in length within
20 mils of each other.
Routing Rules
CLK-to-CMD/ADD Requirements
• Clock signals should match CMD/ADD signals in
length within 20 mils max.
Table A-12. DDR2 Address/Command Signal Group Routing Guidelines (Sheet 2 of 2)
Parameter Routing Guidelines for SODIMM Figure