Revision History
-2 Freescale Semiconductor
Chapter 10
Interrupt
Controller
(INTC)
•In Section 10.5.5.2, “Ensuring Coherency, added the following sentence before GetResource source code:
Processor recognition of interrupts must be enabled before executing the GetResource code sequence.”
•In Section 10.3.1.3, “INTC Interrupt Acknowledge Register (INTC_IACKR), removed the first paragraph from
the note:
“The INTC_IACKR must not be read speculatively while in software vector mode. Therefore, for future
compatibility, the TLB entry covering the INTC_IACKR must be configured to be guarded.”
•In Tabl e 10- 2, added the following note at the end of this table:
“To ensure compatibility with all PowerPC processors, the TLB entry covering the INTC memory map must be
configured as guarded, both in software and hardware vector modes.
•In software vector mode, the INTC_IACKR must not be read speculatively.
•In hardware vector mode, guarded writes to the INTC_CPR or INTC_EOIR complete before the interrupt
acknowledge signal from the processor asserts.
•In Section 10.4.2.1.4, “Priority Comparator Submodule, added the following paragraph to this section:
“One consequence of the priority comparator design is that once a higher priority interrupt is captured, it must be
acknowledged by the CPU before a subsequent interrupt request of even higher priority can be captured. For
example, if the CPU is executing a priority level 1 interrupt, and a priority level 2 interrupt request is captured by
the INTC, followed shortly by a priority level 3 interrupt request to the INTC, the level 2 interrupt must be
acknowledged by the CPU before a new level 3 interrupt will be generated.”
•In Section 10.5.5.2, “Ensuring Coherency, moved the text in Section 10.5.5.2: Ensuring Coherency under a
new “Section 10.5.5.2.1: Interrupt with Blocked Priority”. Added a new “Section 10.5.5.2.2: Raised Priority
Preserved”.
•In Tabl e 10- 9, removed ETPU_MCR[MGEB] and ETPU_MCR[ILFB] from the “Source MPC5553” column
under eTPU_A for hardware vector mode offset 0x0430.
Chapter 11
Frequency
Modulated
Phase Locked
Loop (FMPLL)
and System
Clocks
•In Section 11.4.3.3, “FM Calibration Routine, corrected the equation at the end of the third paragraph: changed
value of M from 640 to 480.
• Updated Figure 11-9 to reflect that bits 23:28 and bits 30:31 are read-only.
•In Section 11.4.3.1, “Programming System Clock Frequency Without Frequency Modulation, added the
following note:
“MFD must be set such that the VCO stays within its valid range with the selected predivider output.”
Chapter 12
External Bus
Interface (EBI)
In Table 12-20, blanked some of the cells in the D0:D7 and D8:D15 (32-Bit Port Size) columns.
Chapter 16
Boot Assist
Module (BAM)
•In Tabl e 16- 2, for the TLB entry 2- EBI region, updated the Physical Base Address to 0x2000_0000.
•In Section 16.3.2.3.2, “CAN and eSCI Configuration, updated the watchdog timer time-out period from 3 x
2^28 system clock cycles to 2^27 system clock cycles.
•In Tabl e 16- 8, updated the Watchdog Timeout period (seconds) entries.
Chapter 17
Enhanced
Modular
Input/Output
Subsystem
(eMIOS)
• Corrected the direction of arrows in
Figure 17-12.
•In Table 17-10, added the sentence “eMIOS channel 6, 7,10, 11, 16, 17, 18, and 19 DMA support is only for
MPC5554.”
Chapter 18
Enhanced Time
Processing Unit
(eTPU)
In Section 18.4.2.2.4, “STAC Bus Configuration Register (ETPU_REDCR) changed SERVER_ID1 and
SERVER_ID2 fields to read-only and SRV1 and SRV2 fields to read-write.
Table A-1. Rev. 4 to Rev. 5 Changes (continued)
Chapter Description
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