Freescale Semiconductor MPC5553 - Page 652

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 17-13
17.3.1.6 eMIOS Channel Counter Register (EMIOS_CCNTRn)
The EMIOS_CCNTRn contains the value of the internal counter. When GPIO mode is selected or the
channel is frozen, the EMIOS_CCNTRn is readable and writable. For all others modes, the
EMIOS_CCNTRn is a read-only register. When entering some operating modes, this register is
automatically cleared (refer to section Section 17.4.4.4, “Modes of Operation of the Unified Channels,”
for details).
17.3.1.7 eMIOS Channel Control Register (EMIOS_CCRn)
The eMIOS_CCRn enables the setting of several control parameters for a unified channel. Among these
controls are the setting of a channel prescaler, channel mode selection, input trigger sensitivity and
filtering, interrupt and DMA request enabling, and output mode control.
WPTA A1 A1 B1 B1
MC – Normal
1
A2 A1 B2 B2
MC – Buffered A2 A1 B2 B2
OPWFM – Normal A2 A1 B2 B1
OPWFM – Buffered A2 A1 B2 B1
OPWMC – Normal A2 A1 B2 B1
OPWMC – Buffered A2 A1 B2 B1
OPWM – Normal A2 A1 B2 B1
OPWM – Buffered A2 A1 B2 B1
1
In these modes, the register EMIOS_CBDRn is not used, but B2 can be accessed.
0123456789101112131415
R00000000 C
W
1
Reset0000000000000000
Reg Addr UCn Base + 0x0008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RC
W
1
Reset0000000000000000
Reg Addr UCn Base + 0x0008
1
In GPIO mode or freeze action, this register is writable.
Figure 17-7. eMIOS Channel Counter Register (EMIOS_CCNTRn)
Table 17-9. EMIOS_CADRn and EMIOS_CBDRn Value Assignments (Continued)