Intel EP80579

Intel
®
EP80579 Integrated Processor Product Line—Schematics Checklist
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
285 Order Number: 320068-005US
NMI I/O
• Terminate to GND using 10KΩ
± 5% resistor if used.
Note:
• This signal should be pulled-down to
GND with a 10KΩ resistor if not
used
SMI_OUT# O
• Pull up signal to Platform 3.3V
(VCC3)
using a 10KΩ ± 5%
resistor
if used
Note:
• This signal can be left as a no
connect (NC) if not used.
• This signal can be exposed via a
testpoint for debug purposes if not
used.
STPCLK_OUT# O
• Can monitor signal using an
LED
• Pull up signal to Platform 3.3V
(VCC3)
using a 10KΩ ± 5%
resistor
if used
Note:
• This signal can be left as a no
connect (NC) if not used.
• This signal can be exposed via a
testpoint for debug purposes if not
used.
RCIN# I
• Connect to Keyboard Reset
(KBDRST#) pin of the Keyboard
Controller provided by the
Super I/O device.
• Pull up signal to Platform 3.3V
(VCC3)
using a 10KΩ ± 5%
resistor.
Note:
• This signal should be pull-up to 3.3V
with a 10KΩ
resistor if not used
A20GATE I
• Connect to A20M pin of the
Keyboard Controller provided
by the Super I/O device.
• Pull up signal to Platform 3.3V
(VCC3) power supply using
10KΩ ± 5% resistor
• Provides an alternative method to
assert A20M#.
Note:
• This signal should be pull-up to 3.3V
with a 10KΩ
resistor if not used.
CPURST# O
• Processor reset output signal
that can be used by a debug
tool.
• Pull up signal to Platform 3.3V
(VCC3)
using a 10KΩ ± 5%
resistor
if used
• Processor Bus Reset: The IMCH
asserts CPURST# while RSTIN# is
asserted and for approximately 1ms
after RSTIN# is deasserted. The
CPURST# allows the processor to
begin execution in a known state.
Note:
• This signal can be left as a no
connect (NC) if not used.
• This signal can be exposed via a
testpoint for debug purposes if not
used.
CPUPWRGD_OUT O (OD)
• Processor Internal Power Good
output signal that can be used
by a debug tool.
• Pull up signal to EP80579 3.3V
(VCC33)
using a 10KΩ ± 5%
resistor
.
• CPU Power Good: This EP80579
output signal is made visible to the
platform for debug purposes only.
This signal is an open drain signal,
and requires an external pull-up
resistor. CPUPWRGD monitors an
internal signal connected directly
form the IICH to the processor and
represents a logical AND of PWROK
and VRMPWRGD signals.
Note:
• Pull up signal to EP80579 3.3V
(VCC33)
using a 10KΩ ± 5% resistor
if not used.
• This signal can be exposed via a
testpoint for debug purposes if not
used.
Table 100. Schematic Checklist (Sheet 2 of 26)
Checklist Items
I/O Type
(Default)
Recommendations Comments