Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—Contents
Intel
®
EP80579 Integrated Processor Product Line May 2010
6 Order Number: 320068-005US
10.1.8 Topology 2 – EP80579 to PCI Express Connector
with Logic Analyzer Connector142
10.1.9 Topology 3 – EP80579 to PCI Express Down Device ......................................... 145
10.1.10 Topology 4 – EP80579 to PCI Express Down Device
with Logic Analyzer Connector ............................................................................ 148
10.2 Additional Considerations for PCI Express....................................................................... 150
10.2.1 PCI Express I/O Devices ..................................................................................... 150
10.2.2 EMI ......................................................................................................................150
10.2.3 PCI Express (JTAG) Boundary Scan Pins........................................................... 151
10.2.4 Terminating Unused PCI Express Ports .............................................................. 151
10.2.5 Probing Differential Pairs ..................................................................................... 151
11.0 Serial ATA (SATA) Interface........................................................................................................ 152
11.1 SATA Interface ................................................................................................................. 152
11.1.1 General Routing and Placement.......................................................................... 152
11.2 SATA Transmit and Receive Signals –
SATA_TXp[1:0], SATA_TXn[1:0], SATA_RXp[1:0], SATA_RXn[1:0] ............................... 154
11.2.1 SATA Trace Separation....................................................................................... 157
11.2.2 SATA Trace Length Guidelines and Pair Matching ............................................. 157
11.2.3 SATA AC Coupling Requirements....................................................................... 158
11.3 SATA General Purpose Signals – SATA1_GP, SATA0_GP ............................................ 158
11.4 SATA Clock Signals – SATA_CLKREFp, SATA_CLKREFn ............................................ 158
11.5 SATA_RBIAS/SATA_RBIAS# Connection ....................................................................... 158
11.6 SATALED# Implementation.............................................................................................. 159
11.7 SATA Host Connector Placement Considerations ........................................................... 159
11.8 Terminating Unused SATA Interface ................................................................................ 162
12.0 Universal Serial Bus (USB) Interface ..........................................................................................164
12.1 USB Interface ................................................................................................................... 164
12.2 Layout Guidelines ............................................................................................................. 164
12.2.1 General Routing and Placement.......................................................................... 164
12.2.2 USB Differential Signals – USBp[1:0], USBn[1:0]................................................ 165
12.2.3 USB_RBIASp/USB_RBIASn Connection ............................................................ 169
12.2.4 Clock signal -- USB CLK48.................................................................................. 170
12.2.5 USB Over Current protection – OC[1:0]# ............................................................ 170
12.3 Plane Splits, Voids, and Cut-Outs (Anti-Etch) .................................................................. 170
12.3.1 Vcc Plane Splits, Voids, and Cut-Outs (Anti-Etch) .............................................. 170
12.3.2 GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) ............................................ 171
12.4 USB Power Line Layout Topology.................................................................................... 171
12.5 EMI Considerations ..........................................................................................................171
12.5.1 Common Mode Chokes ....................................................................................... 171
12.6 ESD .................................................................................................................................. 172
12.7 Front Panel Solutions .......................................................................................................173
12.7.1 Internal USB Cables ............................................................................................ 173
12.7.2 Motherboard/PCB Mating Connector................................................................... 174
12.7.3 Front Panel Daughter Card.................................................................................. 176
12.8 Terminating Unused USB Interface .................................................................................. 176
13.0 System Management Bus (SMBus) Interface ............................................................................. 178
13.1 SMBus 2.0/SMLink Interface ............................................................................................ 178
13.1.1 SMBus Design Considerations ............................................................................ 178

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English