Intel EP80579

May 2010 Intel
®
EP80579 Integrated Processor Product Line
Order Number: 320068-005US 5
Contents—Intel
®
EP80579 Integrated Processor Product Line
7.1.5 CPU (IA-32 core) Only Reset.................................................................................85
7.2 Reset and Powergood Interface Implementation................................................................85
7.2.1 Powergood Interface.............................................................................................. 86
7.2.2 Reset Interface ......................................................................................................86
7.2.3 Reset Sequence ....................................................................................................87
7.3 Power Management............................................................................................................88
7.3.1 Supported Power States ........................................................................................ 88
7.4 Power Sequencing..............................................................................................................90
8.0 Platform System Clock ..................................................................................................................91
8.1 Platform System Clock Generation..................................................................................... 91
8.2 System Clock Groups .........................................................................................................94
8.2.1 HOST_CLK Group.................................................................................................94
8.2.2 CLK100 (SRC Clock) Group ..................................................................................96
8.2.3 CLK33 Group.........................................................................................................99
8.2.4 CLK14 Group.......................................................................................................101
8.2.5 CLK48 Group.......................................................................................................102
8.3 CK410 General Design Guides ........................................................................................103
8.3.1 Clock Driver Decoupling ......................................................................................103
8.3.2 Clock Power Delivery...........................................................................................104
8.3.3 Decoupling Caps and Ferrite Beads ....................................................................104
8.3.4 CK410 Power Plane Filtering...............................................................................106
8.3.5 IREF.....................................................................................................................110
8.3.6 EMI Constraints ...................................................................................................110
9.0 System Memory Interface (DIMM)...............................................................................................111
9.1 Terminology and Definitions .............................................................................................111
9.2 Supported Configurations ................................................................................................. 111
9.3 Rules for Populating DIMM Slots......................................................................................113
9.3.1 Supported Rank Configurations...........................................................................113
9.3.2 DRAM Addressing ...............................................................................................114
9.3.3 DDR2 DIMM Ordering Overview..........................................................................116
9.4 System Memory Design Guidelines..................................................................................117
9.5 Package Length Compensation........................................................................................ 119
9.6 Length Matching and Length Formulas ............................................................................119
9.7 DDR2 Interface System Interconnect ...............................................................................119
9.7.1 Topologies and Routing Guidelines .....................................................................120
9.7.2 Reset Pin Requirement........................................................................................131
9.7.3 DC Bias Signals ...................................................................................................131
9.8 Decoupling Recommendations.........................................................................................134
10.0 PCI Express* Interface ................................................................................................................135
10.1 PCI Express Layout Design Guidelines............................................................................136
10.1.1 Board Stack-Up Consideration ............................................................................137
10.1.2 Impedance Requirements....................................................................................138
10.1.3 AC Coupling Requirements .................................................................................139
10.1.4 Via Requirements ................................................................................................139
10.1.5 Compensation Resistor Signals Guidelines.........................................................140
10.1.6 PCI Express Clocks Routing Guidelines.............................................................. 140
10.1.7 Topology 1 – EP80579 to PCI Express Connector..............................................140