GigaDevice Semiconductor GD32F3x0 - Page 20

GD32F3x0 User Manual
20
CHLEN=0, CKPL=0) ...................................................................................................................... 534
Figure20-44. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1) ...................................................................................................................... 535
Figure 20-45. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0) ...................................................................................................................... 535
Figure 20-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1) ...................................................................................................................... 535
Figure 20-47. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0) ...................................................................................................................... 535
Figure 20-48. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1) ...................................................................................................................... 535
Figure 20-49. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0) ...................................................................................................................... 536
Figure 20-50. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1) ...................................................................................................................... 536
Figure 20-51. Block diagram of I2S clock generator ................................................................... 536
Figure 20-52. I2S initialization sequence ........................................................................................ 538
Figure 20-53. I2S master reception disabling sequence ............................................................ 540
Figure 21-1. HDMI-CEC Controller Block Diagram ....................................................................... 555
Figure 21-2. Start bit ............................................................................................................................ 556
Figure 21-3. Valid data bit ................................................................................................................... 556
Figure 21-4. Signal Free Time ............................................................................................................ 557
Figure 21-5. Error Bit Period .............................................................................................................. 558
Figure 21-6. Bit period long error ..................................................................................................... 559
Figure 21-7. Transmission error detection .................................................................................... 560
Figure 22-1. Block diagram of TSI module ..................................................................................... 571
Figure 22-2. Block diagram of Sample pin and Channel Pin ..................................................... 572
Figure 22-3. Voltage of a sample pin during charge-transfer sequence ................................ 574
Figure 22-4. FSM flow of a charge-transfer sequence ................................................................ 575
Figure 23-1. USBFS block diagram .................................................................................................. 590
Figure 23-2. Connection with host or device mode ..................................................................... 591
Figure 23-3. Connection with OTG mode ....................................................................................... 592
Figure 23-4. State transition diagram of host port ....................................................................... 592
Figure 23-5. HOST mode FIFO space in SRAM ............................................................................. 597
Figure 23-6. Host mode FIFO access register map ..................................................................... 597
Figure 23-7. Device mode FIFO space in SRAM ........................................................................... 598
Figure 23-8. Device mode FIFO access register map ................................................................. 599