GigaDevice Semiconductor GD32F3x0 - Page 19

GD32F3x0 User Manual
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Figure 20-8. Timing diagram of TI master mode with discontinuous transfer ..................... 520
Figure 20-9. Timing diagram of TI master mode with continuous transfer ........................... 520
Figure 20-10. Timing diagram of TI slave mode ........................................................................... 521
Figure 20-11. Timing diagram of NSS pulse with continuous transmit .................................. 522
Figure 20-12. Timing diagram of write operation in Quad-SPI mode ...................................... 523
Figure 20-13. Timing diagram of read operation in Quad-SPI mode ....................................... 524
Figure 20-14. Block diagram of I2S .................................................................................................. 527
Figure 20-15. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ....... 528
Figure 20-16. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ....... 529
Figure 20-17. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ....... 529
Figure 20-18. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ....... 529
Figure 20-19. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ....... 529
Figure 20-20. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ....... 529
Figure 20-21. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ....... 530
Figure 20-22. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ....... 530
Figure 20-23. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ... 530
Figure 20-24. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ... 530
Figure 20-25. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ... 531
Figure 20-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ... 531
Figure 20-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ... 531
Figure 20-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ... 531
Figure 20-29. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ... 531
Figure 20-30. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ... 531
Figure 20-31. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) .... 532
Figure 20-32. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) .... 532
Figure 20-33. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) .... 532
Figure 20-34. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) .... 532
Figure 20-35. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0) ...................................................................................................................... 533
Figure 20-36. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1) ...................................................................................................................... 533
Figure 20-37. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0) ...................................................................................................................... 533
Figure 20-38. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1) ...................................................................................................................... 533
Figure 20-39. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0) ...................................................................................................................... 534
Figure20-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1) ...................................................................................................................... 534
Figure 20-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0) ...................................................................................................................... 534
Figure 20-42. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1) ...................................................................................................................... 534
Figure 20-43. PCM standard long frame synchronization mode timing diagram (DTLEN=00,