GigaDevice Semiconductor GD32F3x0 - Page 18

GD32F3x0 User Manual
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Figure 16-83. Timing chart of up counting mode, PSC=0/2 ....................................................... 437
Figure 16-84. Timing chart of up counting mode, change TIMERx_CAR on the go ........... 437
Figure 17-1. IFRP output timechart 1 ............................................................................................... 444
Figure 17-2. IFRP output timechart 2 ............................................................................................... 445
Figure 17-3. IFRP output timechart 3 ............................................................................................... 445
Figure 18-1. USART module block diagram................................................................................... 448
Figure 18-2. USART character frame (8 bits data and 1 stop bit) ............................................ 449
Figure 18-3. USART transmit procedure ........................................................................................ 451
Figure 18-4. Oversampling method of a receive frame bit (OSB=0) ........................................ 452
Figure 18-5. Configuration step when using DMA for USART transmission ........................ 453
Figure 18-6. Configuration step when using DMA for USART reception ............................... 454
Figure 18-7. Hardware flow control between two USARTs ........................................................ 454
Figure 18-8. Hardware flow control .................................................................................................. 455
Figure 18-9. Break frame occurs during idle state ....................................................................... 456
Figure 18-10. Break frame occurs during a frame ....................................................................... 457
Figure 18-11. Example of USART in synchronous mode ........................................................... 457
Figure 18-12. 8-bit format USART synchronous waveform (CLEN=1) .................................... 458
Figure 18-13. IrDA SIR ENDEC module ........................................................................................... 458
Figure 18-14. IrDA data modulation ................................................................................................. 459
Figure 18-15. ISO7816-3 frame format ............................................................................................. 460
Figure 18-16. USART receive FIFO structure ................................................................................ 462
Figure 18-17. USART interrupt mapping diagram ........................................................................ 464
Figure 19-1. I2C module block diagram .......................................................................................... 484
Figure 19-2. Data validation ............................................................................................................... 485
Figure 19-3. START and STOP signal .............................................................................................. 485
Figure 19-4. Clock synchronization ................................................................................................. 486
Figure 19-5. SDA line arbitration....................................................................................................... 486
Figure 19-6. I2C communication flow with 7-bit address ........................................................... 487
Figure 19-7. I2C communication flow with 10-bit address (Master Transmit) ...................... 487
Figure 19-8. I2C communication flow with 10-bit address (Master Receive) ........................ 487
Figure 19-9. Programming model for slave transmitting (10-bit address mode) ................. 489
Figure 19-10. Programming model for slave receiving (10-bit address mode) .................... 490
Figure 19-11. Programming model for master transmitting (10-bit address mode) ............ 492
Figure 19-12. Programming model for master receiving using Solution A (10-bit address
mode) ............................................................................................................................................... 494
Figure 19-13. Programming model for master receiving mode using solution B (10-bit
address mode) ............................................................................................................................... 496
Figure 20-1. Block diagram of SPI .................................................................................................... 513
Figure 20-2. SPI timing diagram in normal mode ......................................................................... 514
Figure 20-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) ................... 515
Figure 20-4. A typical full-duplex connection ............................................................................... 517
Figure 20-5. A typical simplex connection (Master: receive, Slave: transmit) ..................... 518
Figure 20-6. A typical simplex connection (Master: transmit only, Slave: receive) ............ 518
Figure 20-7. A typical bidirectional connection ............................................................................ 518