GigaDevice Semiconductor GD32F3x0 - Page 207

GD32F3x0 User Manual
207
010: TIMER0 channel0 input capture
011: TIMER0 OCPRE_CLR input
100: TIMER1 channel3 input capture
101: TIMER1 OCPRE_CLR input
110: TIMER2 channel0 input capture
111: TIMER2 OCPRE_CLR input
23
WNDEN
Window mode enable
This bit is used to disconnect the CMP1_IP input of CMP1 from PA3 and connect it
to CMP0’s CMP0_IP input.
0: CMP1_IP is connected to PA3
1: CMP1_IP is connected to CMP0_IP
22:20
CMP1MSEL[2:0]
CMP1_IM input selection
These bits are used to select the source connected to the CMP1_IM input of the
CMP1.
000: V
REFINT
/4
001: V
REFINT
/2
010: V
REFINT
*3/4
011: V
REFINT
100: PA4 (DAC)
101: PA5
110: PA2
111: Reserved
19:18
CMP1M[1:0]
CMP1 mode
These bits are used to control the operating mode of the CMP1.
00: High speed / full power
01: Medium speed / medium power
10: Low speed / low power
11: Very-low speed / ultra-low power
17
Reserved
Must be kept at reset value.
16
CMP1EN
CMP1 enable
0: CMP1 disabled
1: CMP1 enabled
15
CMP0LK
CMP0 lock
This bit allows to have all control bits of CMP0 as read-only. It can only be set once
by software and cleared by a system reset.
0: CMP_CS[15:0] bits are read-write
1: CMP_CS[15:0] bits are read-only
14
CMP0O
CMP0 output
This bit is a copy of CMP0 output state, which is read only.
0: Non-inverting input below inverting input and the output is low