110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller
than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low
when the counter is larger than TIMERx_CH0CV, and high otherwise.
111: PWM mode1. When counting up, O0CPRE is low when the counter is smaller
than TIMERx_CH0CV, and high otherwise. When counting down, O0CPRE is high
when the counter is larger than TIMERx_CH0CV, and low otherwise.
If configured in PWM mode, the O0CPRE level changes only when the output
compare mode is adjusted from “Timing” mode to “PWM” mode or the comparison
result changes.
Channel 0 compare output shadow enable
When this bit is set, the shadow register of TIMERx_CH0CV register, which
updates at each update event, will be enabled.
0: Channel 0 output compare shadow disable
1: Channel 0 output compare shadow enable
The PWM mode can be used without verifying the shadow register only in single
pulse mode (when SPM=1)
Channel 0 output compare fast enable
When this bit is set, the effect of an event on the trigger in input on the
capture/compare output will be accelerated if the channel is configured in PWM0 or
PWM1 mode. The output channel will treat an active edge on the trigger input as a
compare match, and CH0_O is set to the compare level independently from the
result of the comparison.
0: Channel 0 output quickly compare disable.
1: Channel 0 output quickly compare enable.
Channel 0 I/O mode selection
This bit-field specifies the work mode of the channel and the input signal selection.
This bit-field is writable only when the channel is not active. (CH0EN bit in
TIMERx_CHCTL2 register is reset).).
00: Channel 0 is programmed as output mode
01: Channel 0 is programmed as input mode, IS0 is connected to CI0FE0
10: Channel 0 is programmed as input mode, IS0 is connected to CI1FE0
11: Channel 0 is programmed as input mode, IS0 is connected to ITS
Note: When CH0MS[1:0]=11, it is necessary to select an internal trigger input
through TRGS bits in TIMERx_SMCFG register.
Must be kept at reset value.
Channel 0 input capture filter control
The CI0 input signal can be filtered by digital filter and this bit-field configure the
filtering capability.
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