channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF
flag is set, the corresponding interrupt or DMA request is sent if enabled. In
addition, if channel 1 is configured in input mode, the current value of the counter is
captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag
was already high.
0: No generate a channel 1 capture or compare event
1: Generate a channel 1 capture or compare event
This bit can be set by software, and cleared by hardware automatically. When this
bit is set, the counter is cleared. The prescaler counter is cleared at the same time.
0: No generate an update event
1: Generate an update event
Channel control register 0 (TIMERx_CHCTL0)
Address offset: 0x18
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
Must be kept at reset value.
Channel 0 compare output control
This bit-field specifies the compare output mode of the the output prepare signal
O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and
CH0_ON channels polarity depends on CH0P and CH0NP bits.
000: Timing mode. The O0CPRE signal keeps stable, independent of the
comparison between the register TIMERx_CH0CV and the counter TIMERx_CNT.
001: Set the channel output. O0CPRE signal is forced high when the counter is
equals to the output compare register TIMERx_CH0CV.
010: Clear the channel output. O0CPRE signal is forced low when the counter is
equals to the output compare register TIMERx_CH0CV.
011: Toggle on match. O0CPRE toggles when the counter is equals to the output
compare register TIMERx_CH0CV.
100: Force low. O0CPRE is forced to low level.
101: Force high. O0CPRE is forced to high level.
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