GigaDevice Semiconductor GD32F3x0 - Page 358

GD32F3x0 User Manual
358
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CH0OF
Reserved.
CH0IF
UPIF
rc_w0
rc_w0
rc_w0
Bits
Fields
Descriptions
31:10
Reserved
Must be kept at reset value.
9
CH0OF
Channel 0 over capture flag
When channel 0 is configured in input mode, this flag is set by hardware when a
capture event occurs while CH0IF flag has already been set. This flag is cleared by
software.
0: No over capture interrupt occurred
1: Over capture interrupt occurred
8:2
Reserved
Must be kept at reset value.
1
CH0IF
Channel 0 ‘s capture/compare interrupt flag
This flag is set by hardware and cleared by software. When channel 0 is in input
mode, this flag is set when a capture event occurs. When channel 0 is in output
mode, this flag is set when a compare event occurs.
0: No Channel 1 interrupt occurred
1: Channel 1 interrupt occurred
0
UPIF
Update interrupt flag
This bit is set by hardware on an update event and cleared by software.
0: No update interrupt occurred
1: Update interrupt occurred
Software event generation register (TIMERx_SWEVG)
Address offset: 0x14
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CH0G
UPG
w
w
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value.
1
CH0G
Channel 0’s capture or compare event generation
This bit is set by software in order to generate a capture or compare event in