GigaDevice Semiconductor GD32F3x0 - Page 357

GD32F3x0 User Manual
357
event:
The UPG bit is set
The counter generates an overflow or underflow event
The restart mode generates an update event.
1: Update event disable.
Note: When this bit is set to 1, setting UPG bit or restart mode does not generate
an update event, but the counter and prescaler are initialized.
0
CEN
Counter enable
0: Counter disable
1: Counter enable
The CEN bit must be set by software when timer works in external clock, pause
mode and encoder mode.
Interrupt enable register (TIMERx_DMAINTEN)
Address offset: 0x0C
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
CH0IE
UPIE
rw
rw
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value.
1
CH0IE
Channel 0 capture/compare interrupt enable
0: disabled
1: enabled
0
UPIE
Update interrupt enable
0: disabled
1: enabled
Interrupt flag register (TIMERx_INTF)
Address offset: 0x10
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved