GigaDevice Semiconductor GD32F3x0 - Page 440

GD32F3x0 User Manual
440
The restart mode generates an update event.
1: Update event disable.
Note: When this bit is set to 1, setting UPG bit or the restart mode does not
generate an update event, but the counter and prescaler are initialized.
0
CEN
Counter enable
0: Counter disable
1: Counter enable
The CEN bit must be set by software when timer works in external clock, pause
mode and encoder mode.
Control register 1 (TIMERx_CTL1)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
MMC[2:0]
Reserved
rw
Bits
Fields
Descriptions
31:7
Reserved
Must be kept at reset value.
6:4
MMC[2:0]
Master mode control
These bits control the selection of TRGO signal, which is sent in master mode to
slave timers for synchronization function.
000: When a counter reset event occurs, a TGRO trigger signal is output. The
counter resert source:
Master timer generate a reset
The UPG bit in the TIMERx_SWEVG register is set
001: Enable. When a conter start event occurs, a TGRO trigger signal is output.
The counter start source :
CEN control bit is set
The trigger input in pause mode is high
010: When an update event occurs, a TGRO trigger signal is output. The update
source depends on UPDIS bit and UPS bit.
3:0
Reserved
Must be kept at reset value.
Interrupt enable register (TIMERx_DMAINTEN)
Address offset: 0x0C