GigaDevice Semiconductor GD32F3x0 - Page 442

GD32F3x0 User Manual
442
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
UPG
w
Bits
Fields
Descriptions
31:1
Reserved
Must be kept at reset value.
0
UPG
This bit can be set by software, and cleared by hardware automatically. When this
bit is set, the counter is cleared. The prescaler counter is cleared at the same time.
0: No generate an update event
1: Generate an update event
Counter register (TIMERx_CNT)
Address offset: 0x24
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CNT[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
CNT[15:0]
This bit-filed indicates the current counter value. Writing to this bit-filed can change
the value of the counter.
Prescaler register (TIMERx_PSC)
Address offset: 0x28
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved