GigaDevice Semiconductor GD32F3x0 - Page 443

GD32F3x0 User Manual
443
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PSC[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value.
15:0
PSC[15:0]
Prescaler value of the counter clock
The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The
value of this bit-filed will be loaded to the corresponding shadow register at every
update event.
Counter auto reload register (TIMERx_CAR)
Address offset: 0x2C
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CARL[15:0]
rw
Bits
Fields
Descriptions
31:16
Reserved
Must be kept at reset value
15:0
CARL[15:0]
Counter auto reload value
This bit-filed specifies the auto reload value of the counter.