GigaDevice Semiconductor GD32F3x0 - Page 632

GD32F3x0 User Manual
632
0: No resume driven
1: Resume driven
5:4
Reserved
Must be kept at reset value
3
PEDC
Port enable/disable change
Set by the core when the status of the Port enable bit 2 in this register
changes.
2
PE
Port Enable
This bit is automatically set by USBFS after a USB reset signal finishes and
cannot be set by software.
This bit is cleared by the following events:
– A disconnect condition
– Software clearing this bit
0: Port disabled
1: Port enabled
1
PCD
Port connect detected
Set by USBFS when a device connection is detected. This bit can be cleared
by writing 1 to this bit.
0
PCST
Port connect status
0: Device is not connected to the port
1: Device is connected to the port
Host channel-x control register (USBFS_HCHxCTL) (x = 0..7 where x =
channel_number)
Address offset: 0x0500 + (channel_number × 0x20)
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CEN
CDIS
ODDFRM
DAR[6:0]
Reserved
EPTYPE[1:0]
LSD
Reserved
rs
rs
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EPDIR
EPNUM[3:0]
MPL[10:0]
rw
rw
rw
Bits
Fields
Descriptions