GigaDevice Semiconductor GD32F3x0 - Page 633

GD32F3x0 User Manual
633
31
CEN
Channel enable
Set by the application and cleared by USBFS.
0: Channel disabled
1: Channel enabled
Software should following the operation guide to disable or enable a channel.
30
CDIS
Channel disable
Software can set this bit to disable the channel from processing transactions. Software
should follow the operation guide to disable or enable a channel.
29
ODDFRM
Odd frame
For periodic transfers (interrupt or isochronous transfer), this bit controls that whether in
an odd frame or even frame this channel’s transaction is desired to be processed.
0: Even frame
1: Odd frame
28:22
DAR[6:0]
Device address
The address of the USB device that this channel wants to communicate with.
21:20
Reserved
Must be kept at reset value
19:18
EPTYPE[1:0]
Endpoint type
The transfer type of the endpoint that this channel wants to communicate with.
00: Control
01: Isochronous
10: Bulk
11: Interrupt
17
LSD
Low-Speed device
The device that this channel wants to communicate with is a Low-Speed Device.
16
Reserved
Must be kept at reset value
15
EPDIR
Endpoint direction
The transfer direction of the endpoint that this channel wants to communicate with.
0: OUT
1: IN
14:11
EPNUM[3:0]
Endpoint number
The number of the endpoint that this channel wants to communicate with.
10:0
MPL[10:0]
Maximum packet length
The target endpoint’s maximum packet length.
Host channel-x interrupt flag register (USBFS_HCHxINTF) (x = 0..7 where x =
channel number)
Address offset: 0x0508 + (channel_number × 0x20)