GigaDevice Semiconductor GD32F3x0 - Page 635

GD32F3x0 User Manual
635
3
STALL
STALL
A STALL response is received.
2
Reserved
Must be kept at reset value
1
CH
Channel halted
This channel is disabled by a request, and it will not response to other requests during the
request processing.
0
TF
Transfer finished
All the transactions of this channel finish successfully, and no error occurs. For IN
channel, this flag will be triggered after PCNT bits in USBFS_HCHxLEN register reach
zero. For OUT channel, this flag will be triggered when software reads and pops a TF
status entry from the RxFIFO.
Host channel-x interrupt enable register (USBFS_HCHxINTEN) (x = 0..7, where
x = channel number)
Address offset: 0x050C + (channel_number × 0x20)
Reset value: 0x0000 0000
This register contains the interrupt enable bits for the flags in USBFS_HCHxINTF register. If
a bit in this register is set by software, the corresponding bit in USBFS_HCHxINTF register is
able to trigger a channel interrupt. The bits in this register are set and cleared by software.
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DTE
RIE
REQOVRIE
BBERIE
USBERIE
Reserved.
ACKIE
NAKIE
STALLIE
Reserved
CHIE
TFIE
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:11
Reserved
Must be kept at reset value
10
DTERIE
Data toggle error interrupt enable
0: Disable data toggle error interrupt
1: Enable data toggle error interrupt