Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—Revision History
Intel
®
EP80579 Integrated Processor Product Line May 2010
18 Order Number: 320068-005US
June 2009 004
Defeatured LEB Mastering and removed external mastering descriptions related to this in Table 3,
“EP80579 Feature List” and in Section 22.0, “Local Expansion Bus (LEB) Interface”
Corrected ODT setting for single rank from ODT off to 75 ohms in Table 43, “Write Operation ODT
Table”
Changed the following signal names:
•EX_REQ_GNT# to Reserved 19
•EX_SLAVE_CS# to Reserved 20
•EX_GNT_REQ# to NC57
•EX_WAIT# to NC58
• EX_WDTXFER to NC59
Corrected signal name:
• SIU_CST1 to SIU_CST1#
• SIU_CST2 to SIU_CST2#
Section 7.0, “Power Management and Reset Interface”
Section 7.4, “Power Sequencing”
• Deleted Power Sequencing section. Refer to the Intel® EP80579 Integrated Processor Product
Line Datasheet, Document Number 320066 for Power Sequencing Timing Diagrams.
Section 8.0, “Platform System Clock”
Section 8.2.1, “HOST_CLK Group”
• Added statement to indicate that the Host_Clk_Group Topology and Routing guidelines apply
to the routing of two separate 100MHz differential clocks from the CK410 Clock Synthesizer to
EP80579 (CLKP100/CLKN100) and the ITP Port (BLKP/BCLKN)
• Deleted intra-pair routing specification requirements from Table 18, “HOST_CLK Routing
Guidelines”
Section 9.0, “System Memory Interface (DIMM)”
Table 46, “DDR2 Address/Command Signal Group Routing Guidelines”
• Deleted the reference of Control (Ctrl) signals from the Routing Rules of CLK-to-CMD/ADD
Section 22.0, “Local Expansion Bus (LEB) Interface”
Added Section 22.2, “LEB Memory Size (LEB_SIZE) Strapping”
Section 25.0, “Sideband Signals”
Table 92, “Sideband Signals”
• Changed pull-up resistor on CPURST# signal from 4.7K ohm to 10K ohm
• Changed pull-up resistor on IERR# signal from 4.7K ohm to 10K ohm
Section 27.0, “Layout Checklist”
Table 97, “Layout Checklist”
• Deleted intra-pair length matching requirements for the following signals:
CLKP100/CLKN100 and BCLKP/BCLKN
PEA0_Tp[7:0]/PEA0_Tn[7:0]
PEA0_Rp[7:0]/PEA0_Rn[7:0]
• Changed naming of GBEn_CLKOUT to GBEn_TxCLK
• Changed naming of GBEn_CLKIN to GBEn_RxCLK
• Changed Characteristic Impedance (Zo) for EX_CLK(CLK33) signal from 50-ohm to 55-ohm
Section 28.0, “Schematics Checklist”
Table 100, “Schematic Checklist”
• GP27_IRQ39 - Updated power source to Suspend Power Well
• GP33_IRQ33 - Changed backup to bootup for default configuration description
• EX_ADDR[24:0] - Included description for strapping EX_ADDR[23:21] to determine LEB
Memory Size (LEB_SIZE)
• SPKR - Deleted external pull-up requirement on SPKR signal. Signal has a weak internal pull-
down
Date Revision Description

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English