Intel EP80579 Guide

May 2010 Intel
®
EP80579 Integrated Processor Product Line
Order Number: 320068-005US 19
Revision History—Intel
®
EP80579 Integrated Processor Product Line
November 2008 003
Section 7.0, “Power Management and Reset Interface”
Updates:
• Update to Figure 49 to indicate the delay between PWROK and VRMPWRGD to be 102ms
instead of 12ms
• Update to Figure 54 to connect GBE_AUX_PWR_GOOD to SYS_PWR_OK in systems without
Sustain Power.
Section 19.0, “Gigabit Ethernet (GbE) Interface”
Updates:
• Updates to Table 81, Table 82, and Table 83 to include WOL capability for GbE Port 0.
Section 20.0, “IEEE 1588-2008 Hardware Assist Interface”
Updates:
• Termination of ASMSSIG and AMMSSIG signals changed from pull-ups to pull-down
Section 28.0, “Schematics Checklist”
Updates:
• Updates to indicate signal terminations to Core and Suspend Power Wells
• Termination of ASMSSIG and AMMSSIG (IEEE 1588-2008) signals changed from pull-ups to
pull-downs.
September
2008
002
Chapter 9.0, “System Memory Interface (DIMM)”. Updates to:
• Table 27, “Supported DDR2 Device Densities and Widths” on page 111
• Table 28, “Supported DRAM Capacity for 64-bit Mode” on page 112
• Table 29, “Supported DRAM Capacity for 32-bit Mode” on page 112: Termination of unused
DDR2 Data Bus Signals in 32-bit mode
• Table 33, “256Mb Addressing” on page 114, Supported DDR2 memory addressing
configurations
• Table 34, “512Mb Addressing” on page 114, Supported DDR2 memory addressing
configurations
• Table 35, “1Gb Addressing” on page 115, Supported DDR2 memory addressing configurations
• Table 36, “2Gb Addressing” on page 115, Supported DDR2 memory addressing configurations
Chapter 25.0, “Sideband Signals”. Added power-up deactivation pull-ups to sideband signals
CPUSLP_OUT#, CPURST#, and IERR#
Chapter 28.0, “Schematics Checklist”. Termination updates for reserved pins and NC56.
Appendix A, “System Memory Interface (SODIMM)”. Updated Table A-2, “Supported SODIMM
Memory Capacity for 64-bit Mode” on page 317.
Appendix B, “System Memory Interface (Memory Down)”. Updates to:
• Table B-18, “Supported DRAM Capacity for 64-bit Mode” on page 334
• Table B-20, “256Mb Addressing” on page 335, supported DDR2 memory addressing
configurations
• Table B-21, “512Mb Addressing” on page 335, supported DDR2 memory addressing
configurations
• Table B-22, “1Gb Addressing” on page 336, supported DDR2 memory addressing
configurations
• Table B-23, “2Gb Addressing” on page 336, supported DDR2 memory addressing
configurations
August 2008 001 Initial version
Date Revision Description

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English