Intel
®
EP80579 Integrated Processor Product Line—Introduction
Intel
®
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
22 Order Number: 320068-005US
EDMA Enhanced DMA
EMI Electro Magnetic Interference
EMTS Electrical Mechanical Thermal Specification, used for processor specifications.
ESD Electrostatic Discharge
FRU Field Replaceable Unit
FS Full-speed, refers to USB.
FSB Front Side Bus (a common external interface for Intel
®
architecture (IA) processors)
FWH Firmware Hub, a non-volatile memory device used to store the system BIOS.
HBA
Host Bus Adapter, necessary when connecting a peripheral to a computer that doesn’t
have native support for that peripheral’s interface.
HCD Host Controller Device, a USB interface for programmers
HECBASE PCI Express Enhanced Configuration Base Register
HSI High Speed Interface, refers to USB.
IA Intel
®
Architecture instruction set commonly known as “x86”
IA-32 core
High performance processor based on the 32-bit embedded Intel
®
Architecture (IA-32)
processor
I
2
CInter-IC Control
I
2
S Integrated Interchip-Sound
ICE In-Circuit-Emulator- JTAG based Emulator to debug software on an embedded system
ICH I/O Controller Hub
IICH Integrated I/O Controller Hub
IMCH Integrated Memory Controller Hub
I/O
1. Input/Output
2. When used as a qualifier to a transaction type, specifies that transaction targets Intel
®
architecture-specific I/O space (e.g., I/O read).
IP Internet Protocol
ITP-XDP In Target Probe - Expanded Debug Port
JEDEC Joint Electron Device Engineering Council, solid state technology forum
LEB
Local Expansion Bus - EP80579 internal bus to external expansion target devices such as
external memory or other physical layer devices.
LPC Low Pin Count
LS Low-speed, refers to USB.
LSb Least Significant Bit
LSB Least Significant Byte
MCH Memory Controller Hub
MMIO Memory Mapped I/O
MSb Most Significant Bit
MSB Most Significant Byte
MSI Message Signaled Interrupt that encodes interrupts as an in-band 32-bit write transaction.
MTBF Mean Time Between Failures
NCM Non Coherent Memory
NSI
North South Interface, the designation for the proprietary, internal high-speed serial
interconnect between the IMCH and the IICH.
Table 2. Acronyms and Terminology (Sheet 2 of 3)
Acronym Definition
To Next Page
Loading...
Need help?
General
