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Intel EP80579 Guide

Intel EP80579
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Intel
ยฎ
EP80579 Integrated Processor Product Lineโ€”Schematics Checklist
Intel
ยฎ
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
291 Order Number: 320068-005US
GP27_IRQ39 I/O
โ€ข Input/Output configurable if
used as GPIO[27].
โ€ข Can be used as IRQ[39]
โ€ข No external pull-up required if used
in IRQ mode.
Note:
โ€ข Must be pulled high through a 10
Kฮฉ resistor if not used.
โ€ข Resides in Suspend Power Well
GP28_IRQ30 I/O
โ€ข Input/Output configurable if
used as GPIO[28].
โ€ข Can be used as IRQ[30]
โ€ข No external pull-up required if used
in IRQ mode.
Note:
โ€ข Must be pulled high through a 10
Kฮฉ resistor if not used.
โ€ข Resides in Suspend Power Well
GP29_SATA1GP I
โ€ข Input Only if used as GPIO[29]
โ€ข Can be used as SATA Port 1
Interlock switch Status Input
depending on the platform
โ€ขSATA1GP:
Interlock Switch Status Port1:
0 = Closed
1 = Open
โ€ข Must be pulled high through a 10
Kฮฉ resistor if not used.
โ€ข Resides in Core Power Well
GP30_IRQ31 I
โ€ข Input only if used as GPIO[30].
โ€ข Can be used as IRQ[31]
โ€ข No external pull-up required if used
in IRQ mode.
Note:
โ€ข Must be pulled high through a 10
Kฮฉ resistor if not used.
โ€ข Resides in Core Power Well
GP31_IRQ32 I
โ€ข Input only if used as GPIO[31].
โ€ข Can be used as IRQ[32]
โ€ข No external pull-up required if used
in IRQ mode.
Note:
โ€ข Must be pulled high through a 10
Kฮฉ resistor if not used.
โ€ข Resides in Core Power Well
GP33_IRQ33 I/O
โ€ข Input/Output configurable if
used as GPIO[33].
โ€ข Can be strapped for SPI Boot-
up
โ€ข Can be used as IRQ[33]
โ€ข This pin, in conjuction with
GP17_IRQ25, can be strapped
to select the source of BIOS
during boot-up.
โ€ข Since GP17 and GP33 have
internal pull-ups, the default
bootup is set to FWH. GP17 and
GP33 should be strapped to
ground through 1Kฮฉ pull-down
resistors to configure the boot
source to the SPI Flash.
โ€ข This signal can function as either
GPIO[33] or IRQ[33].
โ€ข 50Kฮฉ internal pull-up
Boot BIOS Selection Strap: This strap
selects the source of the BIOS for
system boot.
EP80579 interprets GP17 & GP33
strappings as follows:
GP17 GP33 (Boot Options)
0 0 Boot BIOS from SPI
0 1 Reserved
1 0 Reserved
1 1 (Default) Boot BIOS from LPC
โ€ขSee Table 74 for more details
Table 100. Schematic Checklist (Sheet 8 of 26)
Checklist Items
I/O Type
(Default)
Recommendations Comments

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Intel EP80579 Specifications

General IconGeneral
BrandIntel
ModelEP80579
CategoryComputer Hardware
LanguageEnglish

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