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Intel EP80579 Guide

Intel EP80579
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Intel
ยฎ
EP80579 Integrated Processor Product Lineโ€”Schematics Checklist
Intel
ยฎ
EP80579 Integrated Processor Product Line
Platform Design Guide May 2010
297 Order Number: 320068-005US
SATALED# OD O
โ€ข Can monitor using an LED to
indicate SATA activity.
โ€ข Requires an external 10Kฮฉ pull-
up to EP80579 VCC33 (3.3V)
power supply if used
Serial ATA LED: This is an open-
collector/open-drain output signal
driven during SATA command activity. It
is to be connected to external circuitry
that can provide the current to drive a
platform LED. When active, the LED is
on. When tristated, the LED is off. An
external pull-up resistor is required.
Note:
โ€ข If all SATA ports are not used, this
signal can be left as no connect
(NC)
SATA0GP (GPIO[26]) See General Purpose I/O (GPIO) Interface
SATA1GP (GPIO[29]) See General Purpose I/O (GPIO) Interface
Universal Serial Bus (USB) Interface
USBp[1:0],
USBn[1:0]
I/O
โ€ข No external resistors are
required.
โ€ข Connect USBp/n[0] and USBp/
n[1] differential signal pins
through Common Mode Chokes
to USB connector for ESD and
EMI suppression.
โ€ข Common mode chokes with a target
impedance of 80-90 ฮฉ at 100 MHz
generally provide adequate noise
suppression.
โ€ขSee Section 12.2.2 for more details.
Note:
โ€ข Can be left as no connect (NC)
when the port is not used.
OC[1:0]# I
โ€ข Connect to OC[2:1]# outputs
of a USB current limiter power
distribution switch.
โ€ข Pull up signals to P3V3_AUX
using a 10Kฮฉ ยฑ 5% resistors
โ€ขSee Section 12.2.5
Note:
โ€ข If these signals are not used, pull up
to EP80579 3.3V Standby voltage
(VCCPSUS) with an 10 kฮฉ resistor.
USB_RBIASp
USB_RBIASn
I/O
โ€ข Short signals USB_RBIASp to
USB_RBIASn at package.
โ€ข
Connect shorted signal to a 22.6 ฮฉ
ยฑ1% pull-down resistor to ground
โ€ขSee Section 12.2.3
โ€ข Bias connection is required even if
the USB ports are not used.
CLK48 I
โ€ข Connect to 48 MHz clock
(USB_48) from the CK410
Clock Synthesizer
โ€ข Connect clock through a 33 ฮฉ
ยฑ5% series resistor.
Note:
โ€ขBoth UART_CLK and USB_CLK
(CLK48) use the same clock output
(USB_48) from the CK410 Clock
Synthesizer.
โ€ข Isolate UART_CLK from USB_CLK
(CLK48) through series resistors.
โ€ข Connect CLK48 to a 48 MHz clock
source even if the USB ports are not
used.
โ€ขSee Section 2.3
โ€ขSee Section 8.2.5, โ€œCLK48 Groupโ€
on page 102.
Power Management Interface
PLTRST# O
โ€ข Connect to EP80579 RSTIN#
input.
โ€ข Connect to all Platform devices
that require reset.
Platform Reset: IICH asserts PLTRST#
to reset Platform devices.
Table 100. Schematic Checklist (Sheet 14 of 26)
Checklist Items
I/O Type
(Default)
Recommendations Comments

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Intel EP80579 Specifications

General IconGeneral
BrandIntel
ModelEP80579
CategoryComputer Hardware
LanguageEnglish

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