EasyManuals Logo

Intel EP80579 Guide

Intel EP80579
347 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #306 background imageLoading...
Page #306 background image
Intel
ยฎ
EP80579 Integrated Processor Product Line May 2010
Order Number: 320068-005US 306
Schematics Checklistโ€”Intel
ยฎ
EP80579 Integrated Processor Product Line
EX_CS[7:0]# I/O
โ€ข External Chip Selects for the
Expansion Bus Peripheral
Devices
โ€ข Pull-up to Platform 3.3V (VCC3)
supply through a 10 Kฮฉ ยฑ5%
resistor
Expansion Bus Target Chip Selects: Chip
selects to select Expansion Bus devices.
โ€ข Devices using EX_CS[3:0]# indicate
Data Ready with EX_IOWAIT#
during EP80579 Read accesses
โ€ข Devices using EX_CS[7:4]# indicate
Data Ready with EX_RDY[3:0]#
during EP80579 Read accesses
Note:
โ€ข Must be pulled high through a 10
Kฮฉ resistor when the interface is not
used or connected to an interfacing
device.
EX_DATA[15:0],
EX_WR#
EX_RD#
I/O
โ€ข Bi-directional Expansion Bus
data/ Expansion Write
Command/ Expansion Bus Read
Command.
โ€ข Isolate DATA/ WR#/RD# to
Platform on-board devices from
inbound/outbound devices
using an external data buffer.
โ€ข Buses to all on-board devices
are isolated from each other
using 22ฮฉ ยฑ5% series resistors.
โ€ขSee Section 22.3.4 for more details.
Note: EP80579 requires a 2nSec hold
time during read accesses.
Requires to delay EX_RD#
signal by 2ns(min) if the
interfacing device cannot meet
the Thold=2nSec time required
by EP80579.
Note:
โ€ข Can be left as no connect (NC)
when the interface is not connected
to an interfacing device or not used
EX_IOWAIT# I
โ€ข Data ready/acknowledge from
expansion bus devices
โ€ข Pull-up to Platform 3.3V (VCC3)
supply through a 10 Kฮฉ ยฑ5%
resistor
โ€ข An expansion bus access is halted
when an external device asserts
EX_IOWAIT# and resumes access
from the halted location once the
external device de-asserts
EX_IOWAIT#
โ€ข Expansion Bus Devices using
EX_CS[3:0]# indicate Data Ready
with EX_IOWAIT# during EP80579
Read Accesses.
Note:
โ€ข Must be pulled high through a 10
Kฮฉ resistor when the interface is not
used or connected to an interfacing
device
EX_PARITY[1:0] I/O
โ€ข Byte wide parity protection on
inbound/outbound transfers.
Note:
โ€ข Can be left as no connect (NC)
when the interface is not connected
to an interfacing device or not used
Table 100. Schematic Checklist (Sheet 23 of 26)
Checklist Items
I/O Type
(Default)
Recommendations Comments

Table of Contents

Other manuals for Intel EP80579

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel EP80579 and is the answer not in the manual?

Intel EP80579 Specifications

General IconGeneral
BrandIntel
ModelEP80579
CategoryComputer Hardware
LanguageEnglish

Related product manuals