Intel EP80579 Guide

May 2010 Intel
®
EP80579 Integrated Processor Product Line
Order Number: 320068-005US 9
Contents—Intel
®
EP80579 Integrated Processor Product Line
24.2.1 Serial Peripheral Interface (SPI) ..........................................................................252
24.2.2 Microwire* Interface .............................................................................................253
24.2.3 Board Design Tip .................................................................................................253
25.0 Sideband Signals.........................................................................................................................254
25.1 CPUSLP_OUT#, INIT33V_OUT#, NMI, SMI_OUT#, STPCLK_OUT, RCIN#,
A20GATE, IERR#257
26.0 Debug Port Design Guide............................................................................................................258
26.1 Overview ...........................................................................................................................258
26.2 Terms and Definitions .......................................................................................................258
26.2.1 General Debug Port Overview ............................................................................. 259
26.2.2 Debug Port Design Reviews ................................................................................259
26.2.3 Depopulating XDP for Production Units...............................................................259
26.2.4 General Guidelines ..............................................................................................260
26.2.5 Termination Resistors ..........................................................................................260
26.3 Routing Guidelines ........................................................................................................... 261
26.3.1 JTAG Routing Guidelines ....................................................................................261
26.3.2 Observation Port Routing Guidelines ..................................................................262
26.3.3 Hook Pins Routing Guidelines .............................................................................263
26.3.4 I
2
C (SDA/SCL) Routing Guidelines......................................................................265
26.3.5 Power...................................................................................................................265
26.4 System Connection...........................................................................................................265
26.5 Mechanical Specifications ................................................................................................ 266
27.0 Layout Checklist ..........................................................................................................................268
27.1 Functional Signal Definitions ............................................................................................268
27.2 Layout Checklist ............................................................................................................... 269
27.3 CK410 Layout Checklist ...................................................................................................281
28.0 Schematics Checklist ..................................................................................................................283
28.1 Functional Signal Definitions ............................................................................................283
28.2 Schematic Checklist .........................................................................................................284
28.3 Power Supply Decoupling................................................................................................. 310
28.4 CK410 Schematic Checklist .............................................................................................312
29.0 Reference Design........................................................................................................................315
A System Memory Interface (SODIMM) .........................................................................................316
A.1 Terminology and Definitions .............................................................................................317
A.2 Supported Configurations ................................................................................................. 317
A.3 Differences between Unbuffered SODIMM and Unbuffered DIMM ..................................317
A.4 SODIMM System Memory Design Guidelines ..................................................................318
A.5 Decoupling Recommendations.........................................................................................331
A.6 Clock Delay Programming and Write Levelization............................................................332
B System Memory Interface (Memory Down) .................................................................................333
B.1 Terminology and Definitions .............................................................................................333
B.2 Supported Configurations ................................................................................................. 334
B.3 DRAM Addressing ............................................................................................................335
B.4 DDR2 Signal Groups ........................................................................................................ 336

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English