Intel EP80579 Guide

Intel
®
EP80579 Integrated Processor Product Line—Contents
Intel
®
EP80579 Integrated Processor Product Line May 2010
10 Order Number: 320068-005US
B.5 Supported Memory Configurations ................................................................................... 337
B.6 Overview and Design Considerations............................................................................... 338
Figures
1 Development Board Block Diagram ....................................................................................... 26
2 Development Board Component Placement – Top View ....................................................... 32
3 Development Board Component Placement – Bottom View.................................................. 33
4 PCB Recommended 10-Layer Stack-Up................................................................................ 34
5 Quadrant Layout (Top View) .................................................................................................. 37
6 Quadrant Layout (Bottom View) ............................................................................................. 38
7 Proper Decoupling Capacitor Placement with Respect to Vias.............................................. 40
8 Routing in a Serpentine Manner............................................................................................. 41
9 Serpentine Spacing-Spacing to Reference Plane Height Ratio ............................................. 41
10 Serpentine Line ...................................................................................................................... 42
11 Tied Together for the Same Potential Planes ........................................................................ 43
12 Series Capacitor for Different Potential Planes ...................................................................... 43
13 Stitching Vias Aligned with Signal Vias .................................................................................. 43
14 Stitching for Layer Changes ...................................................................................................43
15 Traces Routed Parallel to Plane............................................................................................. 44
16 Trace Segment Length...........................................................................................................45
17 Trace Mismatch...................................................................................................................... 45
18 Trace Length Mismatch Corners ............................................................................................ 46
19 Routing Examples of the Length Compensation #1 ............................................................... 46
20 Routing Examples of the Length Compensation #2 ............................................................... 47
21 DC Blocking Capacitor ........................................................................................................... 47
22 Spread Spectrum Modulation Profile...................................................................................... 49
23 Impact of Spread Spectrum Clocking on Radiated Emissions ............................................... 50
24 Cancellation of H-fields Through Inverse Currents ................................................................ 50
25 Length Tuning Parameters..................................................................................................... 51
26 Signal Length Solution Space with One Strobe ..................................................................... 52
27 Signal Length Solution with Two Strobes............................................................................... 52
28 Signal Length Solution Space with Furthest Apart Strobes.................................................... 53
29 Signal Length Solution Space with Matched Strobes............................................................. 53
30 Total Signal Length with Two Components............................................................................ 54
31 Package Trace Length Differences ........................................................................................ 55
32 Example of PLC Compensation on the Motherboard............................................................. 56
33 Signal Parallelism................................................................................................................... 57
34 Improper Via Sharing ............................................................................................................. 58
35 Correct Via Connections ........................................................................................................ 59
36 Improper Necking Down.........................................................................................................60
37 Correct Necking Down ........................................................................................................... 61
38 Signal Crossing Plane Splits ..................................................................................................62
39 Development Board Power Delivery Implementation............................................................. 67
40 Voltage Regulator Multi-Phase Topology Example................................................................ 72
41 Buck Voltage Regulator Example........................................................................................... 73
42 High Current Path With Top MOSFET Turned ON ................................................................ 73
43 High Current Path During Abrupt Load Current Changes ...................................................... 74
44 High Current Path With Top and Bottom MOSFETs Turned Off (Dead Time)....................... 74
45 High Current Path With Bottom MOSFET(s) Turned ON ....................................................... 75

Intel EP80579 Specifications

General

Brand	Intel
Model	EP80579
Category	Computer Hardware
Language	English