May 2010 Intel
®
EP80579 Integrated Processor Product Line
Order Number: 320068-005US 11
Contents—Intel
®
EP80579 Integrated Processor Product Line
46 Processor VCCA Decoupling Circuit Topology ......................................................................76
47 Analog/Bandgap Filter Topology ............................................................................................77
48 Filter Frequency Response Specification ...............................................................................79
49 Powergood and Reset Interface.............................................................................................84
50 Reset Sequence.....................................................................................................................86
51 Clock Control States...............................................................................................................88
52 Development Board Clocking Diagram ..................................................................................92
53 Source Shunt Termination......................................................................................................93
54 Trace Spacing for HOST_CLK Clocks ................................................................................... 94
55 Source Clock Topology to Down Devices (Except PCI-E) .....................................................96
56 CLK100 Clock Group (SRC Clock) Topology.........................................................................97
57 Trace Spacing for 100 MHz SRC Clocks ............................................................................... 98
58 33 MHz Clock Relationships ..................................................................................................98
59 Topology for CLK33 to Down Devices ...................................................................................99
60 Trace Spacing for CLK33 (PCICLK) Clock............................................................................. 99
61 Topology for Sharing CLK33 Between Two Down Devices .................................................100
62 Topology for CLK14 .............................................................................................................101
63 Trace Spacing for CLK14 (REFCLK) Clocks........................................................................101
64 Topology for CLK48 Group ..................................................................................................102
65 Trace Spacing for CLK48 (USBCLK) Clocks .......................................................................102
66 Clock Power Groupings for Decoupling / Filtering................................................................104
67 Decoupling and Filtering Per Clock Group ...........................................................................105
68 Ground Flood on Layer 1 Underneath CK410......................................................................107
69 Edge Decoupling Caps – Examples.....................................................................................108
70 Decoupling Capacitors Placement and Connectivity............................................................109
71 DDR-DIMM- Implementation ................................................................................................115
72 Example of One Single-Rank DIMM Population .................................................................. 115
73 Example of Two Single-Rank DIMM Population ..................................................................116
74 Example of Dual-Rank DIMM Population .............................................................................116
75 DDR2 Interfaced System Interconnect.................................................................................119
76 Data Signal Daisy Chain Routing Topology .........................................................................119
77 Data/Mask/Strobe Signal Routing Topology Diagram..........................................................120
78 Example Length Matching for a Data Byte Lane..................................................................122
79 EP80579-to-DIMM Interconnect DDR2 Clock Signals .........................................................123
80 DDR2 Point-to-Point Clock Routing Diagram.......................................................................124
81 DDR2 Control Signals- Implementation ............................................................................... 126
82 Address/Command Daisy Chain With Parallel Termination Topology Diagram...................129
83 DDR_SLWCRES, DDR_RCOMPX, DDV_CRES, & DDR_CRES0 Routing Topology ........131
84 DDR_CRES1 and DDR_CRES2 Signal Connections.......................................................... 131
85 DDR_VREF Generation Example Circuit ............................................................................. 132
86 PCI Express* Interconnect ...................................................................................................135
87 Recommended PCI Express Stripline Trace Width/Spacing................................................137
88 Recommended PCI Express Microstrip Trace Width/Spacing .............................................138
89 PCI Express Compensation Signal Guidelines ....................................................................139
90 PCI Express Connector Routing (EP80579 Transmit) .........................................................140
91 PCI Express Connector Routing (EP80579 Receive) ..........................................................141
92 PCI Express Connector with LAI Connector Routing (EP80579 Transmit)..........................143
93 PCI Express Connector With LAI Connector Routing (EP80579 Receive) ..........................144
94 PCI Express Down Device Routing (EP80579 Transmit).....................................................145
95 PCI Express Down Device Routing (EP80579 Receive)......................................................146
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