Freescale Semiconductor PowerPC e500 Core - TLB0 Configuration Register (TLB0 CFG)

PowerPC e500 Core Family Reference Manual, Rev. 1
2-38 Freescale Semiconductor
Register Model
2.12.4.1 TLB0 Configuration Register (TLB0CFG)
TLB0CFG, shown in Figure 2-27, provides configuration information for TLB0 of the L2 MMU
supplied with this version of the e500 core complex.
Table 2-22 describes the TLB0CFG fields and shows the values for the e500.
SPR 688 Access: Supervisor read-only
32 39 40 43 44 47 48 49 50 51 52 63
R ASSOC MINSIZE MAXSIZE IPROT AVAIL — NENTRY
W
Reset (e500v1) 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 00000100000000
Reset (e500v2) 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 00001000000000
Figure 2-27. TLB Configuration Register 0 (TLB0CFG)
Table 2-22. TLB0CFG Field Descriptions
Bits Name Description
32–39 ASSOC Associativity of TLB0
0x02 Indicates associativity is 2-way set associative (e500v1 only)
0x04 Indicates associativity is 4-way set associative (e500v2 only)
40–43 MINSIZE Minimum page size of TLB0
0x1 Indicates smallest page size is 4 Kbytes
44–47 MAXSIZE Maximum page size of TLB0
0x1 Indicates maximum page size is 4 Kbytes
48 IPROT Invalidate protect capability of TLB0
0 Indicates invalidate protection capability not supported
49 AVAIL Page size availability of TLB0
0 No variable-sized pages available (MINSIZE = MAXSIZE)
50–51 — Reserved, should be cleared.
52–63 NENTRY Number of entries in TLB0
0x100 TLB0 contains 256 entries (e500v1 only)
0x200 TLB0 contains 512 entries (e500v2 only)