Instruction Model
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 3-39
3.3.2 Supervisor-Level Instructions
The Book E architecture includes the structure of the memory management model,
supervisor-level registers, and the interrupt model. This section describes the supervisor-level
instructions implemented by e500.
3.3.2.1 System Linkage Instructions
This section describes the system linkage instructions (see Table 3-27). The user-level sc
instruction lets a user program call on the system to perform a service and causes the processor to
take a system call interrupt. The supervisor-level rfi instruction is used for returning from an
interrupt handler. The rfci instruction is used for critical interrupts; rfmci is used for machine
check interrupts.
Data Cache
Block Touch
for Store
1, 2
dcbtst CT,rA,rB dcbtst can be no-oped by setting HID0[NOPTI]. dcbtst behaves similarly to dcbt, except
that the line-fill request on the bus is signaled as read or read-claim, and the data is
marked as exclusive in the L1 data cache if there is no shared response on the bus. More
specifically, the following cases occur depending on where the block currently exists or
does not exist in the e500.
• dcbtst hits in the L1 data cache. In this case, the dcbtst does nothing and the state of
the block in the cache is not changed. Thus, if the block was in the shared state, a
subsequent store hits on this shared block and incur the associated latency penalties.
• dcbtst misses in the L1 data cache and hits in the L2 cache. In this case, dcbtst
reloads the L1 data cache with the state found in the L2 cache. Again, if the block was
in the shared state in the L2, a subsequent store hits on this shared block and incur the
associated latency penalties.
• dcbtst misses in L1 data cache, L2 caches. In this case, e500 requests the block from
memory with read or read-claim and reload the L1 data cache in the exclusive state. As
subsequent store hits on exclusive and can perform the store to the L1 data cache
immediately.
dcbtst is no-oped if its target address is mapped as write-through.
Instruction
Cache Block
Invalidate
1
icbi rA,rB icbi is broadcast on the bus. It should always be followed by an msync and an isync to
make sure its effects are seen by instruction fetches following the icbi itself.
Instruction
Cache Block
Touch
icbt CT,rA,rB If CT = 0, the e500 treats icbt as a no-op.
If CT = 1, icbt executes as follows:
• For L1 data cache hit-to-modified, icbt performs like a load on the bus; e500 ignores
data (for L2).
• For L1 data cache hit-to-modified—cast out (for L2)
• If NOPTI is 0, icbt does a touch load to the L2 cache.
1
On some implementations, such as the e500, HID1[ABE] must be set to allow management of external L2 caches (for
implementations with L2 caches) as well as other L1 caches in the system.
2
A program that uses dcbt and dcbtst improperly is less efficient. To improve performance, HID0[NOPTI] can be set, which
causes dcbt and dcbtst to be no-oped at the cache. They do not cause bus activity and cause only a 1-clock execution
latency. The default state of this bit is zero, which enables the use of these instructions.
Table 3-26. User-Level Cache Instructions (continued)
Name Mnemonic Syntax Implementation Notes
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